Open Quuxplusone opened 5 years ago
Bugzilla Link | PR41433 |
Status | NEW |
Importance | P enhancement |
Reported by | Roman Lebedev (lebedev.ri@gmail.com) |
Reported on | 2019-04-08 13:41:12 -0700 |
Last modified on | 2019-04-08 14:31:42 -0700 |
Version | trunk |
Hardware | PC Linux |
CC | craig.topper@gmail.com, daan@dsprenkels.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com |
Fixed by commit(s) | |
Attachments | |
Blocks | |
Blocked by | |
See also | PR41429, PR39603 |
This should be very good for x86 perf (replacing 2 ymm memops + a ymm shuffle with 2 xmm memops). Probably helps other targets too.
If we solve bug 41429, we have a vector select in the form of a shuffle in IR. Close enough to scalar select-store patterns to consider as a generic (DSE? earlyCSE?) optimization (see bug 39603) since it always eliminates ops?
If that's too far of a stretch, then we either have to enhance the SDAG load/store splitting/combining or make a custom pass to do this.