Assertion `isSimple() && "Expected a SimpleValueType!"' failed.

[Quuxplusone]

Bugzilla Link	PR41916
Status	RESOLVED FIXED
Importance	P enhancement
Reported by	Alina Sbirlea (alina.sbirlea@gmail.com)
Reported on	2019-05-16 16:03:52 -0700
Last modified on	2019-06-03 01:49:50 -0700
Version	trunk
Hardware	PC All
CC	arnaud.degrandmaison@arm.com, chad.rosier@gmail.com, llvm-bugs@lists.llvm.org, peter@pcc.me.uk, sam.parker@arm.com, silviu.baranga@arm.com, smithp352@googlemail.com, t.p.northover@gmail.com, Ties.Stuij@arm.com, tpr.ll@botech.co.uk
Fixed by commit(s)
Attachments
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Blocked by
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The following reduced testcase fails with the assertion:
include/llvm/CodeGen/ValueTypes.h:253: llvm::MVT llvm::EVT::getSimpleVT()
const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.

=========
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-eabi"

; Function Attrs: nounwind
define void @f() #0 {
entry:
  br label %"for mixed.s0.x"

"for mixed.s0.x":                                 ; preds = %"for mixed.s0.x",
%entry
  %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
  %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02>
  %2 = fptoui <3 x float> %1 to <3 x i8>
  %3 = bitcast i8* undef to <3 x i8>*
  store <3 x i8> %2, <3 x i8>* %3, align 1
  br label %"for mixed.s0.x"
}

attributes #0 = { nounwind }
===========

To reproduce run: llc -O3 reduced.ll

[Quuxplusone]

Relevant stack trace:

#9 0x0000000002e3a97d llvm::EVT::getSimpleVT() const
include/llvm/CodeGen/ValueTypes.h:0:7
#10 0x0000000002e54d8b llvm::SDNode::getSimpleValueType(unsigned int) const
include/llvm/CodeGen/SelectionDAGNodes.h:997:32
#11 0x0000000002e229b4 performFpToIntCombine(llvm::SDNode*,
llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&,
llvm::AArch64Subtarget const*)
lib/Target/AArch64/AArch64ISelLowering.cpp:9207:18
#12 0x0000000002e20ce4
llvm::AArch64TargetLowering::PerformDAGCombine(llvm::SDNode*,
llvm::TargetLowering::DAGCombinerInfo&) const
lib/Target/AArch64/AArch64ISelLowering.cpp:11346:12
#13 0x00000000054bb37d (anonymous
namespace)::DAGCombiner::combine(llvm::SDNode*)
lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1698:16
#14 0x00000000054ba744 (anonymous
namespace)::DAGCombiner::Run(llvm::CombineLevel)
lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1508:18
#15 0x00000000054ba09f llvm::SelectionDAG::Combine(llvm::CombineLevel,
llvm::AAResults*, llvm::CodeGenOpt::Level)
lib/CodeGen/SelectionDAG/DAGCombiner.cpp:20187:3
#16 0x00000000056d20c0 llvm::SelectionDAGISel::CodeGenAndEmitDAG()
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:781:3
#17 0x00000000056d1ca3
llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction,
true, false, void>, false, true>,
llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true,
false, void>, false, true>, bool&)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:699:1
#18 0x00000000056d178b
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:0:7
#19 0x00000000056ceef5
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:496:3
#20 0x0000000002f765e5 (anonymous
namespace)::AArch64DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:57:5

[Quuxplusone]

It looks to me like r356351 (adding the v3i32, v3f32, v5i32 and v5f32 as MVTs) broke some of assumptions in the AArch64 backend (particularly in the pre-legalization DAG combine). It's also strange that given these additions we don't have the v3i8/v5i8/v3i16/v5i16 MVTs.

Sadly, I don't have the bandwidth to work on this at the moment.

[Quuxplusone]

Patch for review: https://reviews.llvm.org/D62734

[Quuxplusone]

Fix committed in rL362365.