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[Simple Register Coalescing] Assertion `VNI && "No live value at use."' failed. #45217

Open Quuxplusone opened 4 years ago

Quuxplusone commented 4 years ago
Bugzilla Link PR46247
Status NEW
Importance P normal
Reported by Jonas Paulsson (paulsson@linux.vnet.ibm.com)
Reported on 2020-06-09 00:56:33 -0700
Last modified on 2021-09-08 07:34:10 -0700
Version trunk
Hardware PC Linux
CC kparzysz@quicinc.com, llvm-bugs@lists.llvm.org, paulsson@linux.vnet.ibm.com, quentin.colombet@gmail.com
Fixed by commit(s)
Attachments tc_nolivevalatuse.ll (436 bytes, text/plain)
tc_crash4_aftercreduce.ll (1060 bytes, text/plain)
Blocks
Blocked by
See also
Created attachment 23592
reduced testcase

I found a test case which which triggered this assert with machine DCE
disabled. In the reduced test case, it seems that the whole block is in fact
dead and it would normally become an empty block after Machine DCE. However, if
run with

llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -o out.s tc_nolivevalatuse.ll -
disable-machine-dce -misched=shuffle

, the RegisterCoalescer deletes a lot of dead defs, but not all of them. Three
instructions remain, and the mischeduler will then be run and trigger the
assert.

It seems that the RegisterCoalescer is not updating data structures correctly
while deleting instructions.

llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:1144: void
llvm::ScheduleDAGMILive::updatePressureDiffs(llvm::ArrayRef<llvm::RegisterMaskPair>):
Assertion `VNI && "No live value at use."' failed.
...
#8 0x000002aa24927b36 llvm::ScheduleDAGMILive::updatePressureDiffs
...
Quuxplusone commented 4 years ago

Attached tc_nolivevalatuse.ll (436 bytes, text/plain): reduced testcase

Quuxplusone commented 2 years ago

Attached tc_crash4_aftercreduce.ll (1060 bytes, text/plain): reduced testcase