Coalescer breaks case with undef lanes


Bugzilla Link	PR47703
Status	NEW
Importance	P enhancement
Reported by	Matt Arsenault (Matthew.Arsenault@amd.com)
Reported on	2020-10-01 09:09:06 -0700
Last modified on	2020-10-01 09:09:06 -0700
Version	trunk
Hardware	PC Linux
CC	llvm-bugs@lists.llvm.org, quentin.colombet@gmail.com
Fixed by commit(s)
Attachments	`broken-undef-lane-use.def` (451 bytes, text/plain)
Blocks
Blocked by
See also

Created attachment 24014
Reduced testcase

This testcase fails the verifier after the register coalescer with "No live
subrange at use". Before the coalescer, we have

---
name: no_live_subrange_at_use
tracksRegLiveness: true
body:             |
  bb.0:
    undef %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
    %0.sub2:vreg_96 = V_MOV_B32_e32 0, implicit $exec
    %1:vreg_96 = COPY killed %0
    $vgpr0 = COPY killed %1.sub0 # Reading undef sub0

...

The coalescer then correctly merges %0 with %1:
# After register coalescing
********** INTERVALS **********
%0 [16r,32r:0)[32r,64r:1)  0@16r 1@32r L000000000000000C [16r,16d:0)  0@16r
L0000000000000030 [32r,32d:0)  0@32r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function no_live_subrange_at_use: NoPHIs, TracksLiveness

0B  bb.0:
16B   undef %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
32B   %0.sub2:vreg_96 = V_MOV_B32_e32 0, implicit $exec
64B   $vgpr0 = COPY %0.sub0:vreg_96

# End machine code for function no_live_subrange_at_use.

*** Bad machine code: No live subrange at use ***
- function:    no_live_subrange_at_use
- basic block: %bb.0  (0x838aa08) [0B;80B)
- instruction: 64B  $vgpr0 = COPY %0.sub0:vreg_96
- operand 1:   %0.sub0:vreg_96
- interval:    %0 [16r,32r:0)[32r,64r:1)  0@16r 1@32r L000000000000000C
[16r,16d:0)  0@16r L0000000000000030 [32r,32d:0)  0@32r weight:0.000000e+00
- at:          64B

If I take the coalesced function and compute fresh live intervals, it appears
to be equivalent, differing only in the slot index numbers:
# %0 [16r,32r:0)[32r,48r:1)  0@16r 1@32r L000000000000000C [16r,16d:0)  0@16r
L0000000000000030 [32r,32d:0)  0@32r weight:0.000000e+00
# RegMasks:
# ********** MACHINEINSTRS **********
# # Machine code for function no_live_subrange_at_use_post: NoPHIs,
TracksLiveness

# 0B    bb.0:
# 16B     undef %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
# 32B     %0.sub2:vreg_96 = V_MOV_B32_e32 0, implicit $exec
# 48B     $vgpr0 = COPY %0.sub0:vreg_96

This also fails the verifier. I would expect this to behave as if there were an
IMPLICIT_DEF of sub0 and sub2 on the first move, in which case this should be
valid MIR. It seems like the live range computation as well as the update done
by the coalescer are consistently wrong in not counting the final copy as a use

Quuxplusone / LLVMBugzillaTest

Coalescer breaks case with undef lanes #46672