Open Quuxplusone opened 3 years ago
Bugzilla Link | PR50584 |
Status | NEW |
Importance | P enhancement |
Reported by | Roman Lebedev (lebedev.ri@gmail.com) |
Reported on | 2021-06-04 15:20:26 -0700 |
Last modified on | 2021-08-13 01:06:38 -0700 |
Version | trunk |
Hardware | PC Linux |
CC | andrea.dibiagio@gmail.com, david.bolvansky@gmail.com, florian_hahn@apple.com, jay.foad@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, matdzb@gmail.com, piotr.sobczak@amd.com, qshanz@cn.ibm.com |
Fixed by commit(s) | |
Attachments | |
Blocks | |
Blocked by | |
See also | PR11302, PR51460 |
Does anyone familiar with MachineScheduler/PostRAScheduler have any thoughts
on the subject? Is this an inherent design problem,
or is this something that can be fixed?
I don't have much to add except that "perf record / perf report" shows llvm::SUnit::addPred pretty high up on the profile. I have seen that before. The last time I looked into it it seemed to be something to do with the way the barrier chain is handled in ScheduleDAGInstrs, but I never got to the bottom of it.
_Bug 51460 has been marked as a duplicate of this bug._