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[InstCombine] Preferred way to mask and splat a single low bit #50272

Open Quuxplusone opened 3 years ago

Quuxplusone commented 3 years ago
Bugzilla Link PR51305
Status NEW
Importance P enhancement
Reported by Roman Lebedev (lebedev.ri@gmail.com)
Reported on 2021-08-02 09:28:43 -0700
Last modified on 2021-08-07 07:33:24 -0700
Version trunk
Hardware PC Linux
CC llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
Fixed by commit(s) rGe71870512fd896bf6cf34e8ae650f4cf20923258
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Blocked by
See also PR51306, PR51259 
While looking at xor part of https://bugs.llvm.org/show_bug.cgi?id=51259
We have two patterns that we don't canonicalize either way:
https://alive2.llvm.org/ce/z/jfCViF
Which one do we prefer? Shifty?
Quuxplusone commented 3 years ago

TBN, not limited to the low bit: https://alive2.llvm.org/ce/z/J9W3vC

Quuxplusone commented 3 years ago

@spatel: any opinion which patter we should choose as canonical?

Quuxplusone commented 3 years ago

I'd go with 'and 1' over 'ashr' for better known bits.

That also looks like what most targets end up with in codegen because DAGCombine tries to convert the shifts into sext-in-reg, and that looks like it is getting lowered to mask+negate by default.

Either way, I do see cases (looked at x86, AArch64, RISCV, PowerPC) where the backend might want to invert it (might save an instruction).

Quuxplusone commented 3 years ago

Added basic canonicalization in e71870512fd896bf6cf34e8ae650f4cf20923258.