In-tree ASIC/FPGA synthesis+techmap for test benches

[sjkelly]

This would be helpful for high-level isolated gate-level tests outside openlane or other open source PDK flows. Examples: https://github.com/YosysHQ/yosys/tree/master/examples/osu035

We would likely need to use open_pdks to get the liberty files for ABC using Skywater.

Uncertainties:

• Powered Verilog
• EDIF to verilog (netgen?)
• GL synth/TB is possible for ASIC. Same for FPGA?
• Prebuilt liberty files?

Slight prerequisite for this is #42 such that we have self-checking test benches.

[sjkelly]

https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd