Unspecified I/O Standard: [...] Problem ports: code[2:0], clk, led, and ok.

Hello,

Ubuntu 20.04.x + Vivado 2022.1 user here (same result on Vivado 2023.1 as well) I recently bought Nitefury board and I am having problems regenerating bitstream from sample project from this repo.

[DRC NSTD-1] Unspecified I/O Standard: 6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

[DRC UCIO-1] Unconstrained Logical Port: 6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

Does anyone have an idea how to get over this? How can I add additional constraints to solve this? Here is the location of mentioned ports:

Clock comes from MIG

Existing constraints are default constraints from this repo, no changes. https://github.com/RHSResearchLLC/NiteFury-and-LiteFury/tree/master/Sample-Projects/Project-0/FPGA/common/Constraints

Thank you for your help.

RHSResearchLLC / NiteFury-and-LiteFury

Unspecified I/O Standard: [...] Problem ports: code[2:0], clk, led, and ok. #59