STM32 f4_f7 ADC sample time register configuration

[sada45]

Hi~ I am learning the ADC sampling in on STM32F722, and I think I find a bug in the file cpu/stm32/periph/adc_f4_f7.c. In function adc_init(), the code setting the sampling time is follows:

  if (adc_config[line].chan >= 10) {
      dev(line)->SMPR1 &= ~(MAX_ADC_SMP << (3 * (adc_config[line].chan - 10)));
      dev(line)->SMPR1 |= MAX_ADC_SMP << (3 * (adc_config[line].chan - 10));
  }
  else {
      dev(line)->SMPR1 &= ~(MAX_ADC_SMP << (3 * adc_config[line].chan));
      dev(line)->SMPR2 |= MAX_ADC_SMP << (3 * adc_config[line].chan);
  }

To my understanding, the code first clear the SMP<chan> bits in the SMPR1 and SMPR2, then set the new value.

When the chan<10, the SMP are all in the SMPR2 register, so the correct code for chan<10 should be:

  if (adc_config[line].chan >= 10) {
          ........
  }
else {
    dev(line)->SMPR2 &= ~(MAX_ADC_SMP << (3 * adc_config[line].chan));
    dev(line)->SMPR2 |= MAX_ADC_SMP << (3 * adc_config[line].chan);
}

[maribu]

Thx for spotting the issue :)

Would you mind to open a pull request with the fix? Feel free to ping me in the pull request