This mainly fixes the behavior when using PC as an operand in ALU ops.
From documentation:
The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead
I'm not 100% sure whether the +12 offset has to be used when PC is used as the first operand (no shift involved with it). But since the documentation doesn't specify I assume the same logic applies to both the first and second operands. This is confirmed by GBATEK.
This PR also adds a check when the value read from the shift register is 0. In this case, the documentation specifies that the value in Rm has to be used as is, without modification.
This mainly fixes the behavior when using
PCas an operand in ALU ops.From documentation:
I'm not 100% sure whether the +12 offset has to be used when
PCis used as the first operand (no shift involved with it). But since the documentation doesn't specify I assume the same logic applies to both the first and second operands. This is confirmed by GBATEK.This PR also adds a check when the value read from the shift register is 0. In this case, the documentation specifies that the value in
Rmhas to be used as is, without modification.