RISCV-on-Microsemi-FPGA / RTG4-Development-Kit

Sample RISC-V Libero projects for the RTG4 Development Kit
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updating to AXI3 from AXI4 (ready for tag v0.2) (fixed) #19

Closed seb-slowik closed 4 years ago

seb-slowik commented 4 years ago

This update removes the previously added glue_logic needed to work with AXI4 configuration This glue_logic is not needed for AXI3