RISCV-on-Microsemi-FPGA / RTG4-Development-Kit

Sample RISC-V Libero projects for the RTG4 Development Kit
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Updated scripted design for Libero v12.3 (tag 12.3-v1.0) (fixed FCCC) #24

Closed seb-slowik closed 4 years ago

seb-slowik commented 4 years ago

This pull-request brings the scripted sample design up to Libero v12.3. It includes all the commits that would otherwise correspond to the following tags: • 12.1-v1.0 • 12.1-v1.1 • 12.2-v1.0 **
• 12.3-v1.0

*This update also fixes an issue with the FCCC clock which rendered the design broken. New programming files have also been attached.

**21-Feb-20 note by KS: Do not tag commit 5c0c58f as a release tag. The FCCC clock issue was introduced while updating the FCCC component version in the .tcl scripts to the version supported by Libero v12.2. No 12.2-v1.0 tag will be created. This issue is fixed in commit ed521d3 - targeting Libero 12.3.