Libero v12.6 update - Githubissues

RISCV-on-Microsemi-FPGA / RTG4-Development-Kit

Sample RISC-V Libero projects for the RTG4 Development Kit

5 stars 7 forks source link

Libero v12.6 update #28

Closed seb-slowik closed 3 years ago

seb-slowik commented 3 years ago

List of changes with this update:

Scripts updated to Libero v12.6
New MIV_RV32 core designs with 2 different configurations
New MIV_RV32IMAF AHB core design
RTG4 SRAM component updated to v1.0.115
Libero cores used in the design are downloaded automatically using the scripts.
Top level .tcl script fixes
Script log output updated
Readmes now show more information
New programming files