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RISCV-on-Microsemi-FPGA / RTG4-Development-Kit

Sample RISC-V Libero projects for the RTG4 Development Kit
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Increasing Speed #9

Closed salmansheikh closed 5 years ago

salmansheikh commented 6 years ago

I ran the dhrystones test program on the single core running at 50 MHz and got this for the final result:

Microseconds for one run through Dhrystone: 40.0 Dhrystones per Second: 25000.0

By comparision, the LEON3FT IP Core (SparcV8) that my colleague has in an RTG4 FPGA board gave an Dhrystones of 50000.0. It was also run from a 100MHz oscillator divided by 2 so , 50 MHz clock. I am trying to see why the RISCV is only half as fast on that test. Also, I tried increasing both the GL0 and GL1 clocks to 100MHz and the design synthesized and programmed but the dhrystone test failed, in fact, I got a error code of 2 from the ftpServer program so it never ran. Any reason why it broke just by doubling the speeds coming out of the RTGCCC IP?

CLappin commented 5 years ago

Hi,

sorry for the delay in getting back to you. Was the design meeting min and max timing at 100Mhz? From the handbook though it does quote a max operating frequency of ~66Mhz for the MIV_RV32IMA_L1_AHB core.

Regards, Ciaran