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RISCV-on-Microsemi-FPGA / SoftConsole

Eclipse based IDE for RISC-V bare metal software development.
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Dhrystone didn't Build on RTG4 (solved). #15

Closed salmansheikh closed 6 years ago

salmansheikh commented 6 years ago

I tried to run the dhrystone elf file that was in the system by default but it didn't seem to do anything. So, I attempted to build it but get this error about objdump not found during the build:

8:01:29 Build of configuration Default for project Dhrystone_RISCV make all riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o riscv_hal/entry.o riscv_hal/entry.S riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o riscv_hal/init.o riscv_hal/init.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o dhry_1.o dhry_1.c dhry_1.c:31:18: warning: conflicting types for built-in function 'malloc' [-Wbuiltin-declaration-mismatch] extern char malloc (); ^~ riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o dhry_2.o dhry_2.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o dhry_stubs.o dhry_stubs.c dhry_stubs.c:13:6: warning: conflicting types for built-in function 'scanf' [-Wbuiltin-declaration-mismatch] void scanf(const char fmt, int n) ^~~~~ dhry_stubs.c: In function 'malloc': dhry_stubs.c:22:15: warning: initialization makes pointer from integer without a cast [-Wint-conversion] void res = sbrk(sz); ^~~~ riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o dhry_printf.o dhry_printf.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o hal/hw_reg_access.o hal/hw_reg_access.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o riscv_hal/syscall.o riscv_hal/syscall.c riscv_hal/syscall.c:245:6: warning: conflicting types for 'write_hex' void write_hex(int fd, uint32_t hex) ^~~~~ riscv_hal/syscall.c:60:5: note: previous implicit declaration of 'write_hex' was here write_hex(STDERR_FILENO, code); ^~~~~ riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o riscv_hal/riscv_hal.o riscv_hal/riscv_hal.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB -c -o riscv_hal/riscv_hal_stubs.o riscv_hal/riscv_hal_stubs.c riscv64-unknown-elf-gcc -DTIME -fno-inline -Wno-implicit -O0 -g -march=rv32im -mabi=ilp32 -fno-common -fno-builtin-printf -fno-toplevel-reorder -I. -I./riscv_hal -I./drivers/CoreGPIO -I./drivers/CoreUARTapb -I./drivers/CoreTimer -I./hal -DMSCC_STDIO_THRU_CORE_UART_APB ./riscv_hal/init.o dhry_1.o dhry_2.o dhry_stubs.o dhry_printf.o ./hal/hw_reg_access.o ./drivers/CoreGPIO/core_gpio.o ./drivers/CoreUARTapb/core_uart_apb.o ./drivers/CoreTimer/core_timer.o ./riscv_hal/entry.o ./riscv_hal/syscall.o ./riscv_hal/riscv_hal.o ./riscv_hal/riscv_hal_stubs.o -o dhrystone.elf -T ./riscv_hal/microsemi-riscv-ram.ld -nostdlib -nostartfiles -lc -lgcc -L./riscv_hal objdump --source --all-headers --demangle --line-numbers --wide "Dhrystone.elf" > "Dhrystone.lst" **c:/microsemi/softconsole_v5.3/eclipse/../build_tools/bin/sh: objdump: not found make: [Makefile:62: dhrystone.lst] Error 127 (ignored)**

AntonKrug commented 6 years ago

I can't exactly replicate your problem, but even on my side it's not building properly. Looks the project needs to be re-done/fixed.

salmansheikh commented 6 years ago

I got it to build. What I did is changed the following lines in the Makefile from objcopy and objdump to the those below.

ELF_TO_IHEX = riscv64-unknown-elf-objcopy -O ihex --set-start 0 ELF_TO_LST = -riscv64-unknown-elf-objdump --source --all-headers --demangle --line-numbers --wide "Dhrystone.elf" > "Dhrystone.lst"

The program runs but prints a bunch of garbage in the terminal (as shown at the bottom of this post). I suspect it has to do with the original design and thee lines in the Readme.md

### ## Target hardware

This example project is targeted at a SmartFusion2 M2S150 advanced development kit. The example project is built using a clock frequency of 83MHz. Trying to execute this example project on a different design will result in incorrect baud rate being used by CoreUART and timer load value.**

I found an 83MHz referenced in the file dhry_stubs.c and changed it to 5000000 but still no joy.

long time(void) { unsigned long t; asm volatile ("csrr %0, mcycle" : "=r" (t)); // Assumes processor is at 100MHz and that you want time in ms. return t / 50000000; // was 83000000 }

|2r8~Âr> ¼~B>ÌN>²¼ |²ÂN ¾@B>~²¾>N °@B>Âr>°òN>²¼Ì 0? BÀ 0c@°@B>Âr>°òN>²¼²¼ ?²Âr8~ÂB 0

                                                                       0
salmansheikh commented 6 years ago

I got it! In the file sample_hw_platform.h and changed it to from 83000000UL to 50MHz and after changing it and recompiling.

define SYS_CLK_FREQ 50000000UL

And now it runs as shown:

Dhrystone Benchmark, Version 2.1 (Language: C)

Program compiled without 'register' attribute

Please give the number of runs through the benchmark: Execution starts, 100000 runs through Dhrystone Execution ends

Final values of the variables used in the benchmark:

Int_Glob: 5 should be: 5 Bool_Glob: 1 should be: 1 Ch_1_Glob: A should be: A Ch_2_Glob: B should be: B Arr_1_Glob[8]: 7 should be: 7 Arr_2_Glob[8][7]: 100010 should be: Number_Of_Runs + 10 Ptr_Glob-> Ptr_Comp: -2147443216 should be: (implementation-dependent) Discr: 0 should be: 0 Enum_Comp: 2 should be: 2 Int_Comp: 17 should be: 17 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Next_Ptr_Glob-> Ptr_Comp: -2147443216 should be: (implementation-dependent), same as above Discr: 0 should be: 0 Enum_Comp: 1 should be: 1 Int_Comp: 18 should be: 18 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Int_1_Loc: 5 should be: 5 Int_2_Loc: 13 should be: 13 Int_3_Loc: 7 should be: 7 Enum_Loc: 1 should be: 1 Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING should be: DHRYSTONE PROGRAM, 1'ST STRING Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING should be: DHRYSTONE PROGRAM, 2'ND STRING

Microseconds for one run through Dhrystone: 40.0 Dhrystones per Second: 25000.0

salmansheikh commented 6 years ago

How can we update the repo for RTG4 version of this dhrystone program. Seems like some build variables for which platform would be needed to be added to build for that platform as I think this git repo is generic.

AntonKrug commented 6 years ago

  1. Looks like the makefile needs to be updated for the build to work. Good investigation.

  2. The issue with the UART is documented in the readme of the project, users are expected to update the code depending on their design. This has nothing to do with RTG4 as it can run multiple designs with different clocks and the RTG4 specific example would have to be updated the same way as the generic example.

The example project is built using a clock frequency of 83MHz. Trying to execute this example project on a different design will result in incorrect baud rate being used by CoreUART and timer load value.

This example project can be used with another design using a different clock configuration. This can be achieved by overwriting the content of this example project's "hw_platform.h" file with the correct data from your Libero design.