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RISCV-on-Microsemi-FPGA / riscv-hal

RISC-V Hardware Abstraction Layer
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entry.S initialization of mideleg and medeleg causes trap #3

Open redengin opened 4 years ago

redengin commented 4 years ago

other microsemi versions of entry.S::handle_reset do not use csrwi mideleg, 0 csrwi medeleg, see https://github.com/RISCV-on-Microsemi-FPGA/Operating-Systems/blob/master/FreeRTOS/FreeRTOS_on_Mi-V_Processor/miv-rv32im-freertos-port-test/riscv_hal/entry.S#L38

upon csrwi mideleg, 0 entry.S::trap_entry is executed, and riscv_hal.c::handle_trap calls _exit as there is no match.

kevinscully100 commented 4 years ago

This repo contains v2.0 of the RISC-V HAL. This repo has not been kept up to date with the latest versions of the RISC-V HAL, which are currently released via the Microsemi Firmware Catalog.

The latest released version of the RISC-V HAL is v2.2 and is available from the Microsemi Firmware Catalog. This is the version that is used in the example projects in the RTOS repos.

Of course none of this answers your question, but it may bring you closer to an answer. @nitindeshpande any insights?

nitindeshpande commented 4 years ago

This repo contains v2.0 of the RISC-V HAL. This repo has not been kept up to date with the latest versions of the RISC-V HAL, which are currently released via the Microsemi Firmware Catalog.

The latest released version of the RISC-V HAL is v2.2 and is available from the Microsemi Firmware Catalog. This is the version that is used in the example projects in the RTOS repos.

  • Note: you are better off going to the individual RTOS repo of interest (linked from the Operating-Systems repo README.md) than to the subtree folders within the Operating-Systems repo. The individual RTOS repos may contain more up to date code.

Of course none of this answers your question, but it may bring you closer to an answer. @nitindeshpande any insights?

That's correct Kevin, => The latest released version of the RISC-V HAL is v2.2 and is available from the Microsemi Firmware Catalog.