Tweak SPI FIFOs to meet timing better

[barawn]

The diciest timing in the design seems to reliably be the SPI RX/TX FIFOs and they don't actually have to be as big/fast as they are. The TX FIFO can probably be a large wb_clk FIFO coupled with a smaller cross-clock FIFO since it can only output 37.5 MB/s anyway.

[barawn]

@cozzyd 2 questions:

1. do you use the TX fifo count (control register 6, should be 0x18 offset from the SPI base) for anything?
2. what do you set the spitx_full_threshold (the thing that triggers the prog_full output, which I believe is an interrupt) to?

If I split the FIFO up into a big buffer + small clock cross FIFO, the prog_full will only count data in the big buffer and not that clock cross, so functionally there will be a "minimum size" on the threshold (as in if you set it to 1, it might require 33 bytes to hit that threshold). And the TX fifo count obviously won't count anything in the clock cross FIFO so it'd be off a bit as well.

[cozzyd]

1. the TX FIFO count can be printed out as a diagnostic but is otherwise not used for anything.
2. I don't remember where this came from, but looks like it's set to 512. Code is here: https://github.com/RNO-G/librno-g/blob/master/src/radiant.c#L1950 (note the fallthrough)

[barawn]

OK, it doesn't look like either of those will matter, then, and besides you can just drop the FIFO count down to like, 480 or something and it'd be functionally identical.

The TX fifo is the only one with the extra logic so it's probably the only one that needs to be split. Not high priority but want to leave this here in case timing becomes more of a problem later.