[Issue]: how to close or bypass L1 cache

ROCm / HIP

HIP: C++ Heterogeneous-Compute Interface for Portability

https://rocmdocs.amd.com/projects/HIP/

MIT License

3.71k stars 528 forks source link

[Issue]: how to close or bypass L1 cache #3506

Open JNYXR opened 3 months ago

JNYXR commented 3 months ago

Problem Description

MI100 how to close or bypass L1 cache

Operating System

ubuntu 18.04

CPU

AMD EPYC 7452 32-Core Processor

GPU

AMD Instinct MI100

ROCm Version

ROCm 5.5.0

ROCm Component

No response

Steps to Reproduce

No response

(Optional for Linux users) Output of /opt/rocm/bin/rocminfo --support

No response

Additional Information

No response

b-sumner commented 3 months ago

@JNYXR your situation is not clear to me. But if you are writing HIP source code, then I would recommend using __builtin_nontemporal_{load, store}. This will work on all targets.

JNYXR commented 3 months ago

@b-sumner Thank you for your reply，CUDA can set the -Xptxas-dlcm = cg-Xptxas-dscm =wt compiler option to bypass L1 CACHE. Does HIP have compiler options or environment variables? I want to verify whether L1 CACHE affects my kernel, so I want to try bypass L1 CACHE.