RRZE-HPC / pycachesim

Python Cache Hierarchy Simulator
GNU Affero General Public License v3.0
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Consider Write Allocate Misses not as LOADs #9

Open cod3monk opened 4 years ago

cod3monk commented 4 years ago

Currently a Write Allocate Miss leads to a LOAD on the same cache level. This in-turn produces a LOAD and MISS in the statics.

A better solution would be to produce a LOAD in the corresponding load_from cache and inject the cacheline into the current level.