GPIO vector [0] and [43] input are shorted with the output

[M0stafaRady]

The input to vector_gpio_in[21:20] are connected to vector_gpio_out rather than the external GPIOs. Is this intended ? @RTimothyEdwards can you please take a look ? https://github.com/RTimothyEdwards/caravel_openframe_project/blob/main/verilog/rtl/picosoc.v#L653

[RTimothyEdwards]

Yes, that's an error. Please fix it; it's obvious that there should only be cpu_gpio_in entries connecting to gpio_vector_in and cpu_gpio_out entries connecting to gpio_vector_out. I think my testbench may have only checked the first 20 entries; the rest of them overlap with special functions and are a bit more difficult to set up.

[RTimothyEdwards]

Since this repository is in my personal github space, I'll go ahead and push the fix.

[RTimothyEdwards]

Okay, I have pushed the fix.

[M0stafaRady]

Thank you