Need reset synchronization

[RTimothyEdwards]

The openframe project fails one testbench where the CPU fails to start up after bringing the chip out of SPI reset. Both the RESETB pin and the SPI reset need to be synchronized to the core clock.

Since the housekeeping SPI resets only on the POR signal, then there is no problem simply synchronizing the core reset to the core clock. The implementation should allow the reset to be set at any time, but the reset should only be released in synchronization with the clock (on the falling edge, to give a clock half-cycle time between reset release and the next clock positive edge).

The implementation should be: all_resetb = (RESETB pin & SPI resetb) ; core_resetb = (all_resetb & all_resetb_sync) where all_resetb_sync is all_resetb passed through two flops clocked by the inverse of the core clock, and reset to zero on porb.

[RTimothyEdwards]

Actually the reset is synchronized (in the clock_routing.v file). It just incorrectly uses the clock positive edge instead of the clock negative edge (clock_routing.v line 128).