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RTimothyEdwards / magic

Magic VLSI Layout Tool
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DRC errors in block-level but not top-level #141

Open nmoroze opened 2 years ago

nmoroze commented 2 years ago

I have a hierarchical design in Sky130 where Magic is flagging DRC errors for the block-level GDS, but not the top-level that integrates that GDS with a padring. I'm curious why this might be the case, since I figure those errors should be flagged for the top-level as well.

I've attached a tarball with sufficient contents to reproduce this issue. replay-core.sh runs DRC on the block-level (asic_core.gds), and I see this returning 30 DRC violations. replay-top.sh runs DRC on the top-level (asic_top.gds), and it returns no DRC violations. I've tested this on current master, 083c0c10e9a090a00e266575d81d487e11d2cb98.

I'm also curious why these violations are being reported in the first place - they are all met3 spacing violations, and seem to be pointing to connections to the pins of an OpenRAM macro and the rest of my design. However, these connections are intended, and the design is LVS clean.

Any insight you have would be helpful, thanks!

magic-repro.tar.gz

nmoroze commented 2 years ago

Actually, to amend my statement: I realized I'm now seeing LVS errors in the top-level, but not in the core. I haven't yet had a chance to investigate further, but they seem unrelated to the issue at hand (it seems to have to do with nodes that appear only in the top-level, not the core).