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RTimothyEdwards / netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
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Unconnected unmatched ports cause mismatch. Unmatched subckts only partially flattened. #29

Open d-m-bailey opened 2 years ago

d-m-bailey commented 2 years ago

From slack channel discussion https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1628746152015600

netgen 1.5.196

During device level LVS comparison, proxy nets are created for unmatched ports. This can happen when a layout has 2 or more unconnected power nets of the same name that magic extracts as vdd, vdd_uq01, etc. netgen will flatten these cells and hopefully get a match at a higher level in the hierarchy.

However, when the unmatched port is unconnected, the proxy nets are apparently never resolved and cause net count mismatches.

The attached file contains an example using the storage macro of mpw2 caravel.

run_lvs_ok.sh contains fixes to the netlist and setup file to yield a match. run_lvs_ng.sh runs lvs using the default setup file and does not match for 3 reasons.

  1. The control_logic_r subckt had been totally flattened in the layout, but only automatic flattening during lvs was only partially done. 
    
Subcircuit summary:
Circuit 1: control_logic_r                 |Circuit 2: control_logic_r
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8 (87)               |sky130_fd_pr__pfet_01v8 (5) **Mismatch**
sky130_fd_pr__nfet_01v8 (87)               |sky130_fd_pr__nfet_01v8 (5) **Mismatch**
(no matching element)                      |dff_buf_0 (1)
(no matching element)                      |pinv_6 (1)
(no matching element)                      |pinv_0 (1)
(no matching element)                      |pand2_0 (2)
(no matching element)                      |pdriver_2 (1)
(no matching element)                      |pand3_0 (1)
(no matching element)                      |pinv_20 (45)
(no matching element)                      |pnand2_1 (1)
(no matching element)                      |pdriver_5 (1)
Number of devices: 174 **Mismatch**        |Number of devices: 64 **Mismatch**
Number of nets: 102 **Mismatch**           |Number of nets: 65 **Mismatch**
---------------------------------------------------------------------------------------
Flattening instances of pinv_0 in cell control_logic_r makes a better match
Flattening instances of pinv_6 in cell control_logic_r makes a better match
Flattening instances of pinv_20 in cell control_logic_r makes a better match
Flattening instances of pnand2_1 in cell control_logic_r makes a better match
Making another compare attempt.
Subcircuit summary: Circuit 1: control_logic_r Circuit 2: control_logic_r
sky130_fd_pr__pfet_01v8 (87) sky130_fd_pr__pfet_01v8 (54) Mismatch
sky130_fd_pr__nfet_01v8 (87) sky130_fd_pr__nfet_01v8 (54) Mismatch
(no matching element) dff_buf_0 (1)
(no matching element) pand2_0 (2)
(no matching element) pdriver_2 (1)
(no matching element) pand3_0 (1)
(no matching element) pdriver_5 (1)
Number of devices: 174 Mismatch Number of devices: 114 Mismatch
Number of nets: 102 Mismatch Number of nets: 66 Mismatch

NET mismatches: Class fragments follow (with fanout counts):

The netlists can be made to match by adding the following to the netgen setup file.

flatten class dff_buf_array_0 "-circuit2 dff_buf_0" flatten class pand2_0 "-circuit2 pdriver_0" flatten class pand3_0 "-circuit2 pdriver_4"

flatten class control_logic_r "-circuit2 dff_buf_array_0" flatten class control_logic_r "-circuit2 pdriver_6" flatten class control_logic_r "-circuit2 pinv_0" flatten class control_logic_r "-circuit2 pand2_0" flatten class control_logic_r "-circuit2 pdriver_2" flatten class control_logic_r "-circuit2 pand3_0" flatten class control_logic_r "-circuit2 delay_chain" flatten class control_logic_r "-circuit2 pnand2_1" flatten class control_logic_r "-circuit2 pdriver_5"

Is netgen capable of recursively flattening subckts?

2. The previously reported magic bug that does not connect some nets with multiple texts. i.e. vdd, vdd_uq1023, etc.
The `run_lvs_ok.sh` script uses `sed` to correct this.

3. Unconnected unmatched ports causing unmatched net counts. 
There are 2 subckts extracted from the layout that have ports that are not connected inside the subckt.
`sky130_fd_bd_sram__openram_dp_cell_dummy` has an unconnected VDD. (I had to comment out the parasitics.)

.subckt sky130_fd_bd_sram__openram_dp_cell_dummy VDD BL0 BL1 BR0 BR1 GND WL0 WL1 a_38_n79#

.subckt precharge_1 bl br en_bar vdd VSUBS Xpmos_m1_w0_550_sli_dli_0 br vdd en_bar vdd VSUBS pmos_m1_w0_550_sli_dli Xpmos_m1_w0_550_sli_dli_1 vdd bl en_bar vdd VSUBS pmos_m1_w0_550_sli_dli Xpmos_m1_w0_550_sli_dli_2 br bl en_bar vdd VSUBS pmos_m1_w0_550_sli_dli .ends

Adding the following to the setup file yields a match.

flatten class precharge_array "-circuit1 precharge_0" flatten class precharge_array_0 "-circuit1 precharge_1" flatten class port_data "-circuit1 precharge_array" flatten class port_data_0 "-circuit1 precharge_array_0" flatten class dummy_array "-circuit1 sky130_fd_bd_sramopenram_dp_cell_dummy" flatten class replica_column "-circuit1 sky130_fd_bd_sram__openram_dp_cell_dummy" flatten class replica_column "-circuit1 sky130_fd_bd_sramopenram_dp_cell_replica" flatten class replica_column_0 "-circuit1 sky130_fd_bd_sramopenram_dp_cell_dummy" flatten class replica_column_0 "-circuit1 sky130_fd_bd_sramopenram_dp_cell_replica" flatten class replica_bitcell_array "-circuit1 dummy_array" flatten class replica_bitcell_array "-circuit2 dummy_array" flatten class bitcell_array "-circuit1 sky130_fd_bd_sramopenram_dp_cell" flatten class bitcell_array "-circuit2 sky130_fd_bd_sramopenram_dp_cell"



[netgen_float_196.tar.gz](https://github.com/RTimothyEdwards/netgen/files/6974380/netgen_float_196.tar.gz)
d-m-bailey commented 2 years ago

@RTimothyEdwards You may also notice that the log files have tens of thousands of lines that merely say Bad.. Probably a debugging statement that was not deleted.