Non symmetric processing

[d-m-bailey]

@RTimothyEdwards

In tcltk/netgen.tcl.in at line 563

               if {([lsearch $noflat [lindex $endval 0]] == -1) &&
                        ([lsearch $noflat [lindex $endval 1]] == -1)} {
                   netgen::log put "  Flattening non-matched subcircuits $endval\n\n"
                   netgen::flatten class "[lindex $endval 0] $fnum1"
                   netgen::flatten class "[lindex $endval 1] $fnum2"
               } else {
                   netgen::log put "  Continuing with black-boxed subcircuits $endval\n\n"
                   lappend matcherr [lindex $endval 0]
                   # Match pins

but at line 612

            if {([lsearch $noflat [lindex $endval *1*]] == -1) &&
                    ([lsearch $noflat [lindex $endval 1]] == -1)} {
               netgen::log put "  Flattening non-matched subcircuits $endval\n\n"
               netgen::flatten class "[lindex $endval 0] $fnum1"
               netgen::flatten class "[lindex $endval 1] $fnum2"
            } else {
               netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
               lappend matcherr [lindex $endval 0]
??? duplicate ???
               netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
               lappend matcherr [lindex $endval 0]
               # Match pins

The *1* should be a 0, correct? (I added the * for emphasis, they're not in the code). Also are the lines after ??? duplicate ??? correct?

What do you think about appending the file number to matcherr? (at both places)

Suggested fixes for code line 612

            if {([lsearch $noflat [lindex $endval 0]] == -1) &&
                    ([lsearch $noflat [lindex $endval 1]] == -1)} {
               netgen::log put "  Flattening non-matched subcircuits $endval\n\n"
               netgen::flatten class "[lindex $endval 0] $fnum1"
               netgen::flatten class "[lindex $endval 1] $fnum2"
            } else {
               netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
               lappend matcherr [lindex $endval 0]"(1)"
               lappend matcherr [lindex $endval 1]"(2)"
               # Match pins

I'm looking into some other cosmetic changes to this program and can include these if that's ok.

[RTimothyEdwards]

All good observations and suggestions. I just implemented all of them and pushed an update.

[d-m-bailey]

@RTimothyEdwards The file numbers can be confusing. In the compare section of the lvs log, they're referred to as circuit1 and circuit2, but when flattening at the beginning of the log they're referred to as (0) and (1).

Flattening unmatched subcell sky130_fd_io__tk_em1o in circuit sky130_fd_io__com_pdpredrvr_pbias (1)(2 instances)
Flattening unmatched subcell sky130_fd_io__tk_em1s in circuit sky130_fd_io__com_pdpredrvr_pbias (1)(4 instances)
Flattening unmatched subcell sky130_fd_io__com_pdpredrvr_pbiasv2 in circuit sky130_fd_io__gpiov2_pdpredrvr_strong (0)(1 instance)
Flattening unmatched subcell sky130_fd_io__feascom_pupredrvr_nbiasv2 in circuit sky130_fd_io__gpio_pupredrvr_strongv2 (0)(1 instance)

Which is consistent when appending to matcherr?

Also, you may have implemented/corrected it already, but the code block at line 563 looks like only the first cell name is saved to matcherr.

[d-m-bailey]

Not specifically tested, but these changes appear to be working. May suggest addition of file numbers to other messages later.