RTimothyEdwards / netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
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Pin matching (discussion) #40

Closed d-m-bailey closed 2 years ago

d-m-bailey commented 2 years ago

Observations:

RTimothyEdwards commented 2 years ago

Intuitively, it seems like you should be able to match pins on a mismatching topology. In practice, I'm not sure how easy that would be. It might be possible to scan the matched 1:1 partitions for pins and dump those results and mark all of the pins that show up in illegal partitions as "unresolved" or something like that.

d-m-bailey commented 2 years ago

Currently, I'm printing the port correspondence of unmatched subcircuits for the top subcircuit only. Lower cell processing is the same as before - port correspondence is only printed for topologically matching circuits.

d-m-bailey commented 2 years ago

Moved to discussions