Open d-m-bailey opened 2 years ago
d-m-bailey
commented
2 years ago The work around is, of course, to read verilog child modules before they are referenced.
Problems can be detected with grep 'Creating placeholder cell definition for module' on the output log (NOT the lvs log).
RTimothyEdwards
commented
4 months ago @d-m-bailey : I believe that netgen version 1.5.270 fixes this issue. I used the same approach (pretty much the same code) that I used to deal with the same problem of order of input files when mixing verilog and SPICE. Appears to work correctly on the example that Kareem Farid posted recently.
It appears that the order of the verilog files effects the connectivity.
If the parent verilog is read before the child verilog, a placeholder is created. When the actual verilog is input, the ports do not align correctly. I'll attach a minimal test case later, but here are the results of a comparison.
The incorrect results are on the left and the correct results are on the right. Particularly notice the pfet bulk connection to vssd.
Pin 4 (mprj_logic_high_lv/sky130_fd_pr__pfet_g5v0d10v5:1/4) = vssd (port of mgmt_protect)