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RTimothyEdwards / netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
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Unsymmetrical reduction of parameters causes size mismatch. #74

Open d-m-bailey opened 1 year ago

d-m-bailey commented 1 year ago

netgen 1.5.253

When the layout and source have differing hierarchy, the parallel/series parameters resulting from merging devices sometimes do not match. For example, from the gf180mcu SRAM macro, the layout is extracted totally flattened and the source is the calibre extracted cdl with hierarchy.

...
Flattening unmatched subcell Cell_array32x1 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(16 instances)
Flattening unmatched subcell ICV_5 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(64 instances)
Flattening unmatched subcell ICV_4 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(128 instances)
Flattening unmatched subcell 018SRAM_cell1_2x in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(256 instances)
Flattening unmatched subcell ICV_1 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(1 instance)
Flattening unmatched subcell ICV_2 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(8 instances)
Flattening unmatched subcell ICV_1 in circuit gf180mcu_fd_ip_sram__sram256x8m8wm1 (1)(16 instances)

Class gf180mcu_fd_ip_sram__sram256x8m8wm1 (0):  Merged 1 parallel devices.
Class gf180mcu_fd_ip_sram__sram256x8m8wm1 (1):  Merged 69 parallel devices.
Subcircuit summary:
Circuit 1: gf180mcu_fd_ip_sram__sram256x8m8wm1                          |Circuit 2: gf180mcu_fd_ip_sram__sram256x8m8wm1
------------------------------------------------------------------------|------------------------------------------------------------------------
pmos_6p0 (7198->6006)                                                   |pmos_6p0 (6223->6006)
nmos_6p0 (11107->10386)                                                 |nmos_6p0 (10445->10386)
Number of devices: 16392                                                |Number of devices: 16392
Number of nets: 6036                                                    |Number of nets: 6036
-------------------------------------------------------------------------------------------------------------------------------------------------
Resolving symmetries by property value.
Resolving symmetries by pin name.
Netlists match with 107 symmetries with property errors.
nmos_6p0:102 vs. nmos_6p0:M28:
 w circuit1: 0.0001474   circuit2: 0.001474   (delta=164%, cutoff=1%)
nmos_6p0:3241 vs. saout_R_m2:1267/sa:5/nmos_6p0:M1:
 w circuit1: 1.364e-05   circuit2: 6.82e-06   (delta=66.7%, cutoff=1%)
Circuit 1 parallel/series network does not match Circuit 2
Circuit 1 instance nmos_6p0:3241 network:
  M = 1
  l = 6e-07
  w = 1.364e-05
Circuit 2 instance saout_R_m2:1267/sa:5/nmos_6p0:M1 network:
  m = 1
  W = 6.82e-06
  L = 6e-07
  m = 2
  W = 3.41e-06
  L = 6e-07
nmos_6p0:1334 vs. saout_m2:1203/sa:5/nmos_6p0:M1:
 w circuit1: 1.364e-05   circuit2: 6.82e-06   (delta=66.7%, cutoff=1%)
Circuit 1 parallel/series network does not match Circuit 2
Circuit 1 instance nmos_6p0:1334 network:
  M = 1
  l = 6e-07
  w = 1.364e-05
Circuit 2 instance saout_m2:1203/sa:5/nmos_6p0:M1 network:
  m = 1
  W = 6.82e-06
  L = 6e-07
  m = 2
  W = 3.41e-06
  L = 6e-07
nmos_6p0:252 vs. saout_R_m2:1268/sa:5/nmos_6p0:M1:
 w circuit1: 1.364e-05   circuit2: 6.82e-06   (delta=66.7%, cutoff=1%)
Circuit 1 parallel/series network does not match Circuit 2
Circuit 1 instance nmos_6p0:252 network:
  M = 1
  l = 6e-07
  w = 1.364e-05
Circuit 2 instance saout_R_m2:1268/sa:5/nmos_6p0:M1 network:
  m = 1
  W = 6.82e-06
  L = 6e-07
  m = 1
  W = 6.82e-06
  L = 6e-07
nmos_6p0:213 vs. wen_v2:1327/nfet_05v0_I20:48/nmos_6p0:M0:
 w circuit1: 1.92e-06   circuit2: 1.92e-05   (delta=164%, cutoff=1%)
nmos_6p0:10836 vs. wen_v2:1327/nfet_05v0_I20:49/nmos_6p0:M0:
 w circuit1: 1.92e-06   circuit2: 1.92e-05   (delta=164%, cutoff=1%)
pmos_6p0:96 vs. pmos_6p0:M868:
 l circuit1: 3.94e-06   circuit2: 2.365e-06   (delta=50%, cutoff=1%)
 w circuit1: 0.00036234   circuit2: 0.0001638   (delta=75.5%, cutoff=1%)
pmos_6p0:96 vs. pmos_6p0:M868:
 l circuit1: 2.37e-06   circuit2: 3.94e-06   (delta=49.8%, cutoff=1%)
 w circuit1: 0.00016416   circuit2: 0.00036267   (delta=75.4%, cutoff=1%)
pmos_6p0:966 vs. pmos_6p0:M909:
 w circuit1: 0.000368   circuit2: 0.003674   (delta=164%, cutoff=1%)
pmos_6p0:185 vs. saout_m2:1200/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:2744 vs. saout_m2:1201/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:7483 vs. saout_R_m2:1265/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:649 vs. saout_R_m2:1266/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:241 vs. saout_m2:1202/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:6917 vs. saout_m2:1203/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:1625 vs. saout_R_m2:1267/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:72 vs. saout_R_m2:1268/sacntl_2:2/pmos_6p0:M16:
 w circuit1: 4.09e-06   circuit2: 4.09e-05   (delta=164%, cutoff=1%)
pmos_6p0:340 vs. saout_m2:1200/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:9407 vs. saout_m2:1201/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:1095 vs. saout_R_m2:1265/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:4898 vs. saout_R_m2:1266/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:396 vs. saout_m2:1202/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:79 vs. saout_m2:1203/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:9052 vs. saout_R_m2:1267/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:6276 vs. saout_R_m2:1268/sacntl_2:2/pmos_6p0:M22:
 w circuit1: 2.72e-06   circuit2: 2.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:1375 vs. pmos_6p0:M899:
 w circuit1: 1.25e-05   circuit2: 0.0001248   (delta=164%, cutoff=1%)
pmos_6p0:1690 vs. wen_v2:1327/pfet_05v0_I05:46/pmos_6p0:M0:
 w circuit1: 4.72e-06   circuit2: 4.72e-05   (delta=164%, cutoff=1%)
pmos_6p0:9362 vs. wen_v2:1327/pfet_05v0_I05:47/pmos_6p0:M0:
 w circuit1: 4.72e-06   circuit2: 4.72e-05   (delta=164%, cutoff=1%)

Most errors are off by a factor of 10, but some appear swapped.

pmos_6p0:96 vs. pmos_6p0:M868:
 l circuit1: 3.94e-06   circuit2: 2.365e-06   (delta=50%, cutoff=1%)
 w circuit1: 0.00036234   circuit2: 0.0001638   (delta=75.5%, cutoff=1%)
pmos_6p0:96 vs. pmos_6p0:M868:
 l circuit1: 2.37e-06   circuit2: 3.94e-06   (delta=49.8%, cutoff=1%)
 w circuit1: 0.00016416   circuit2: 0.00036267   (delta=75.4%, cutoff=1%)

Actually, that looks like there are 2 property records for the same devices 96 and M686. Symmetrical nets appear to be matched by size and then by name, but sometimes it looks like there might be errors in both.

Test data is the same as https://github.com/RTimothyEdwards/magic/issues/243 lvs.flatten.report will contain the size errors at the top level with no topology errors. lvs.noflatten.report will contain size and port errors at the sram macro level.

This relates to the discussion here.