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RTimothyEdwards / netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
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False negative errors #83

Closed marwaneltoukhy closed 1 year ago

marwaneltoukhy commented 1 year ago

I came across a false negative error that didn't show up in the LVS report. Not sure if this is the best place to file this issue.

ISSUE: openframe example has a pico macro inside it, the GND on met5 wasn't connected from the top level to the macro because of an issue in PnR. This didn't show up as an open circuit in the LVS report, what I think happened is that the GND is shorted in the substrate layer, and because the macro didn't have a subcut layer around it, it wasn't caught in LVS. The error did show up when I ran soft checks, not the full transistor level LVS.

REPRODUCIBLE Repo: https://github.com/efabless/caravel_openframe_project/commits/physical_views branch: physical_views commit: 9256ebd04c2eaa350f8b5d3f29834bba7256b1fc

RTimothyEdwards commented 1 year ago

That is not an LVS error, and definitely not a netgen error. How substrate connections are handled is up to the extraction. Soft connections through the substrate (or a well) is considered an ERC error and should be checked for by a tool like Mitch Bailey's CVC (which extracts the layout without soft connections).

There is no such thing as a "soft" connection in a netlist. The netlist either has connections or it doesn't. Netgen can only tell you whether the netlists are the same or not.

d-m-bailey commented 1 year ago

Actually, CVC runs on the same extracted netlist that is used for LVS.

The "program" that checks for soft connections is a different animal entirely.

RTimothyEdwards commented 1 year ago

@d-m-bailey : Thanks for the clarification, and I apologize for misrepresenting CVC. The general gist of the response is still valid, though.