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RTimothyEdwards / open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
http://opencircuitdesign.com/open_pdks
Apache License 2.0
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Qflow GUI #143

Open buraktoker opened 3 years ago

buraktoker commented 3 years ago

Hello everyone,

I am newbie to Qflow and open source VLSI flow. I have a question about Qflow and this pdk.

Is there any way to see and use these libraries in qflow_gui "Preparation" part like OSU_035 ?

RTimothyEdwards commented 3 years ago

The best way is to have a symbolic link called "tech" in the same directory as you create a project that is a link to the qflow setup in sky130A; e.g., for the default install, ln -s /usr/share/pdk/sky130A/libs.tech/qflow tech. Make this symbolic link before you run qflow gui, and you should be able to see all of the digital standard cell libraries in the qflow GUI.

A word of warning: The high-density standard cells do not work very well with qflow; it will generate a lot of DRC errors. Use the "HS", "MS", and "LS" libraries to minimize the number of DRC issues (I have not had the time to debug some of the more common problems, but the number of DRC errors is manageable for small-ish designs).

buraktoker commented 3 years ago

Hello, Thanks a lot for your reply. However, when I used openpdk libs synthesis gives me an error. Synth.log is shown below. If I used OSU018,this error didn't happen.

Qflow synthesis logfile created on Sal Ağu 10 19:49:45 +03 2021 Running yosys for verilog parsing and synthesis yosys -s fulladder.ys

/----------------------------------------------------------------------------\ yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2016 Clifford Wolf clifford@clifford.at
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

----------------------------------------------------------------------------/

Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

-- Executing script file `fulladder.ys' --

  1. Executing Liberty frontend. Imported 376 cell types from liberty file.

  2. Executing Verilog-2005 frontend. Parsing Verilog input from /home/burakt/Desktop/ASIC/adder2/source/adder.v' to AST representation. Generating RTLIL representation for module\fulladder'. Generating RTLIL representation for module `\rippe_adder'. Successfully finished Verilog frontend.

  3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy.. Top module: \fulladder

3.1.2. Analyzing design hierarchy.. Top module: \fulladder Removing unused module `\rippe_adder'. Removed 1 unused modules.

3.2. Executing PROC pass (convert processes to netlists).

3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases.

3.2.3. Executing PROC_INIT pass (extract init attributes).

3.2.4. Executing PROC_ARST pass (detect async resets in processes).

3.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).

3.2.7. Executing PROC_DFF pass (convert process syncs to FFs).

3.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

3.3. Executing OPT_EXPR pass (perform const folding).

3.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.5. Executing CHECK pass (checking for obvious problems). checking module fulladder.. found and reported 0 problems.

3.6. Executing OPT pass (performing simple optimizations).

3.6.1. Executing OPT_EXPR pass (perform const folding).

3.6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fulladder.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

3.6.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \fulladder. Performed a total of 0 changes.

3.6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.6.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.6.8. Executing OPT_EXPR pass (perform const folding).

3.6.9. Finished OPT passes. (There is nothing left to do.)

3.7. Executing WREDUCE pass (reducing word size of cells).

3.8. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module fulladder: created 0 $alu and 0 $macc cells.

3.9. Executing SHARE pass (SAT-based resource sharing).

3.10. Executing OPT pass (performing simple optimizations).

3.10.1. Executing OPT_EXPR pass (perform const folding).

3.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fulladder.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

3.10.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \fulladder. Performed a total of 0 changes.

3.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.10.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.10.8. Executing OPT_EXPR pass (perform const folding).

3.10.9. Finished OPT passes. (There is nothing left to do.)

3.11. Executing FSM pass (extract and optimize FSM).

3.11.1. Executing FSM_DETECT pass (finding FSMs in design).

3.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

3.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

3.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

3.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

3.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

3.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

3.12. Executing OPT pass (performing simple optimizations).

3.12.1. Executing OPT_EXPR pass (perform const folding).

3.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.12.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.12.5. Finished fast OPT passes.

3.13. Executing MEMORY pass.

3.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

3.13.2. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).

3.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.15. Executing OPT pass (performing simple optimizations).

3.15.1. Executing OPT_EXPR pass (perform const folding).

3.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.15.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.15.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.15.5. Finished fast OPT passes.

3.16. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

3.17. Executing OPT pass (performing simple optimizations).

3.17.1. Executing OPT_EXPR pass (perform const folding).

3.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fulladder.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

3.17.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \fulladder. Performed a total of 0 changes.

3.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.17.6. Executing OPT_RMDFF pass (remove dff with constant values).

3.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.17.8. Executing OPT_EXPR pass (perform const folding).

3.17.9. Finished OPT passes. (There is nothing left to do.)

3.18. Executing TECHMAP pass (map to technology primitives).

3.18.1. Executing Verilog-2005 frontend. Parsing Verilog input from <techmap.v>' to AST representation. Generating RTLIL representation for module_90_simplemap_bool_ops'. Generating RTLIL representation for module \_90_simplemap_reduce_ops'. Generating RTLIL representation for module_90_simplemap_logic_ops'. Generating RTLIL representation for module \_90_simplemap_compare_ops'. Generating RTLIL representation for module_90_simplemap_various'. Generating RTLIL representation for module \_90_simplemap_registers'. Generating RTLIL representation for module_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module \_90_shift_shiftx'. Generating RTLIL representation for module_90_fa'. Generating RTLIL representation for module \_90_lcu'. Generating RTLIL representation for module_90_alu'. Generating RTLIL representation for module \_90_macc'. Generating RTLIL representation for module_90_alumacc'. Generating RTLIL representation for module \$__div_mod_u'. Generating RTLIL representation for module\$__div_mod'. Generating RTLIL representation for module \_90_div'. Generating RTLIL representation for module_90_mod'. Generating RTLIL representation for module \_90_pow'. Generating RTLIL representation for module_90_pmux'. Generating RTLIL representation for module `_90_lut'. Successfully finished Verilog frontend. Mapping fulladder.$xor$/home/burakt/Desktop/ASIC/adder2/source/adder.v:6$1 ($xor) with simplemap. Mapping fulladder.$xor$/home/burakt/Desktop/ASIC/adder2/source/adder.v:7$2 ($xor) with simplemap. Mapping fulladder.$and$/home/burakt/Desktop/ASIC/adder2/source/adder.v:8$3 ($and) with simplemap. Mapping fulladder.$and$/home/burakt/Desktop/ASIC/adder2/source/adder.v:9$4 ($and) with simplemap. Mapping fulladder.$or$/home/burakt/Desktop/ASIC/adder2/source/adder.v:10$5 ($or) with simplemap. No more expansions possible.

3.19. Executing OPT pass (performing simple optimizations).

3.19.1. Executing OPT_EXPR pass (perform const folding).

3.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.19.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.19.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

3.19.5. Finished fast OPT passes.

3.20. Executing ABC pass (technology mapping using ABC).

3.20.1. Extracting gate netlist of module \fulladder' to/input.blif'.. Extracted 5 gates and 8 wires to a netlist network with 3 inputs and 2 outputs.

3.20.1.1. Executing ABC. Running ABC command: berkeley-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_library /stdcells.genlib ABC: Entered genlib library with 15 gates from file "/stdcells.genlib". ABC: + retime -o ABC: + map ABC: Warning: The network was strashed and balanced before mapping. ABC: + write_blif /output.blif

3.20.1.2. Re-integrating ABC results. ABC RESULTS: NAND cells: 1 ABC RESULTS: NOT cells: 1 ABC RESULTS: OAI3 cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 1 ABC RESULTS: internal signals: 3 ABC RESULTS: input signals: 3 ABC RESULTS: output signals: 2 Removing temp directory.

3.21. Executing OPT pass (performing simple optimizations).

3.21.1. Executing OPT_EXPR pass (perform const folding).

3.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

3.21.3. Executing OPT_RMDFF pass (remove dff with constant values).

3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder.. removing unused non-port wire \w1. removing unused non-port wire \w2. removing unused non-port wire \w3. removed 3 unused temporary wires.

3.21.5. Finished fast OPT passes.

3.22. Executing HIERARCHY pass (managing design hierarchy).

3.22.1. Analyzing design hierarchy.. Top module: \fulladder

3.22.2. Analyzing design hierarchy.. Top module: \fulladder Removed 0 unused modules.

3.23. Printing statistics.

=== fulladder ===

Number of wires: 8 Number of wire bits: 8 Number of public wires: 5 Number of public wire bits: 5 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 5 $NAND 1 $NOT 1 $OAI3 1 $XNOR 1 $XOR 1

3.24. Executing CHECK pass (checking for obvious problems). checking module fulladder.. found and reported 0 problems.

  1. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). cell sky130_fd_sc_hsdfxtp_1 (noninv, pins=3, area=27.17) is a direct match for cell type $_DFFP. cell sky130_fd_sc_hs__dfrtn_1 (noninv, pins=4, area=36.76) is a direct match for cell type $_DFFNN0. cell sky130_fd_sc_hsdfrtp_1 (noninv, pins=4, area=36.76) is a direct match for cell type $_DFFPN0. cell sky130_fd_sc_hsdfstp_1 (noninv, pins=4, area=36.76) is a direct match for cell type $_DFFPN1. cell sky130_fd_sc_hs__dfbbn_1 (noninv, pins=6, area=44.76) is a direct match for cell type $_DFFSRNNN. cell sky130_fd_sc_hsdfbbp_1 (noninv, pins=6, area=43.16) is a direct match for cell type $_DFFSRPNN. create mapping for $_DFFNP0 from mapping for $_DFFNN0. create mapping for $_DFFPP0 from mapping for $_DFFPN0. create mapping for $_DFFPP1 from mapping for $_DFFPN1. create mapping for $_DFFSRNPN from mapping for $_DFFSRNNN. create mapping for $_DFFSRPPN from mapping for $_DFFSRPNN. create mapping for $_DFFSRNNP from mapping for $_DFFSRNNN. create mapping for $_DFFSRNPP from mapping for $_DFFSRNNP. create mapping for $_DFFSRPNP from mapping for $_DFFSRPNN. create mapping for $_DFFSRPPP from mapping for $_DFFSRPNP. create mapping for $_DFFNN1 from mapping for $_DFFNN0. create mapping for $_DFFNP1 from mapping for $_DFFNN1. create mapping for $_DFFN from mapping for $_DFFP. final dff cell mappings: sky130_fd_sc_hsdfxtp_1 _DFFN (.CLK(~C), .D( D), .Q( Q)); sky130_fd_sc_hs__dfxtp_1 _DFFP (.CLK( C), .D( D), .Q( Q)); sky130_fd_sc_hsdfrtn_1 _DFFNN0 (.CLK_N( C), .D( D), .Q( Q), .RESET_B( R)); sky130_fd_sc_hsdfrtn_1 _DFFNN1 (.CLK_N( C), .D(~D), .Q(~Q), .RESET_B( R)); sky130_fd_sc_hs__dfrtn_1 _DFFNP0 (.CLK_N( C), .D( D), .Q( Q), .RESET_B(~R)); sky130_fd_sc_hsdfrtn_1 _DFFNP1 (.CLK_N( C), .D(~D), .Q(~Q), .RESET_B(~R)); sky130_fd_sc_hsdfrtp_1 _DFFPN0 (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); sky130_fd_sc_hsdfstp_1 _DFFPN1 (.CLK( C), .D( D), .Q( Q), .SET_B( R)); sky130_fd_sc_hsdfrtp_1 _DFFPP0 (.CLK( C), .D( D), .Q( Q), .RESET_B(~R)); sky130_fd_sc_hsdfstp_1 _DFFPP1 (.CLK( C), .D( D), .Q( Q), .SET_B(~R)); sky130_fd_sc_hsdfbbn_1 _DFFSRNNN (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); sky130_fd_sc_hs__dfbbn_1 _DFFSRNNP (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B(~R), .SET_B( S)); sky130_fd_sc_hsdfbbn_1 _DFFSRNPN (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B(~S)); sky130_fd_sc_hs__dfbbn_1 _DFFSRNPP (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B(~R), .SET_B(~S)); sky130_fd_sc_hsdfbbp_1 _DFFSRPNN (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); sky130_fd_sc_hsdfbbp_1 _DFFSRPNP (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B(~R), .SET_B( S)); sky130_fd_sc_hsdfbbp_1 _DFFSRPPN (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B(~S)); sky130_fd_sc_hsdfbbp_1 _DFFSRPPP (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B(~R), .SET_B(~S)); Mapping DFF cells in module `\fulladder':

  2. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).

5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fulladder.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

5.4. Executing OPTREDUCE pass (consolidate $*mux and $reduce* inputs). Optimizing cells in module \fulladder. Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fulladder'. Removed a total of 0 cells.

5.6. Executing OPT_RMDFF pass (remove dff with constant values).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fulladder..

5.8. Executing OPT_EXPR pass (perform const folding).

5.9. Finished OPT passes. (There is nothing left to do.)

  1. Executing ABC pass (technology mapping using ABC).

6.1. Extracting gate netlist of module \fulladder' to/input.blif'.. Extracted 5 gates and 8 wires to a netlist network with 3 inputs and 2 outputs.

6.1.1. Executing ABC. Running ABC command: /usr/local/share/qflow/bin/yosys-abc -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: ABC: + read_blif /input.blif ABC: + read_lib -w /usr/share/pdk/sky130A/libs.ref/sky130_fd_sc_hs/lib/sky130_fd_sc_hsff_n40C_1v95.lib ABC: Parsing finished successfully. Parsing time = 1.36 sec ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hsdecap_4" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hsdecap_8" without logic function. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfbbn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfbbn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfbbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfrbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfrbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfrtn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfrtp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfrtp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfrtp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfsbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfsbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfstp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfstp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfstp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfxbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfxbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfxtp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdfxtp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dfxtp_4". ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hsdlclkp_1" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hsdlclkp_2" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hs__dlclkp_4" without logic function. ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrbn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrbn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dlrbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrbp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrtn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dlrtn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrtn_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrtp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dlrtp_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlrtp_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlxbn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dlxbn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlxbp_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlxtn_1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hs__dlxtn_2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlxtn_4". ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hsdlxtp_1". ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hs__ebufn_1". ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hsebufn_2". ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hs__ebufn_4". ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hs__ebufn_8". ABC: Scl_ERROR: ABC: execution of command "/usr/local/share/qflow/bin/yosys-abc -s -f /tmp/yosys-abc-jb9MQs/abc.script 2>&1" failed: return code 134. outputprep failure: No file fulladder_mapped.blif. Premature exit. Synthesis flow stopped due to error condition.

RTimothyEdwards commented 3 years ago

@buraktoker : I think your main problem is that you're using qflow version 1.3 which is completely deprecated and unsupported.