DFFLIBMAP error

[1347806]

i am a freashman about qflow. I want try use qflow to synthesize the foo.v with tcbn65lpbwp12tlvttc.lib which is provided by TSMC. Below is script

!/usr/bin/env yosys

read_verilog -sv foo.v hierarchy -top foo proc; opt; techmap; opt dfflibmap -liberty /home/yanan/ic_design/tt/tcbn65lpbwp12tlvttc.lib abc -liberty /home/yanan/ic_design/tt/tcbn65lpbwp12tlvttc.lib

and there is verilog code module foo ( input a, input b, input c, output o );

assign o = (a & b) | c;

endmodule

and there is log

/----------------------------------------------------------------------------			yosys -- Yosys Open SYnthesis Suite
Copyright (C) 2012 - 2016 Clifford Wolf clifford@clifford.at
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

----------------------------------------------------------------------------/

Yosys 0.7 (git sha1 61f6811, gcc 6.2.0-11ubuntu1 -O2 -fdebug-prefix-map=/build/yosys-OIL3SR/yosys-0.7=. -fstack-protector-strong -fPIC -Os)

-- Executing script file `foo.ys' --

Executing Verilog-2005 frontend. Parsing SystemVerilog input from foo.v' to AST representation. Generating RTLIL representation for module \foo'. Successfully finished Verilog frontend.

Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy.. Top module: \foo

2.2. Analyzing design hierarchy.. Top module: \foo Removed 0 unused modules.

Executing PROC pass (convert processes to netlists). 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases.

3.3. Executing PROC_INIT pass (extract init attributes).

3.4. Executing PROC_ARST pass (detect async resets in processes).

3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.6. Executing PROC_DLATCH pass (convert process syncs to latches).

3.7. Executing PROC_DFF pass (convert process syncs to FFs).

3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches.

Executing OPT pass (performing simple optimizations). 4.1. Executing OPT_EXPR pass (perform const folding).

4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

4.4. Executing OPTREDUCE pass (consolidate $mux and $reduce inputs). Optimizing cells in module \foo. Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

4.6. Executing OPT_RMDFF pass (remove dff with constant values).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo..

4.8. Executing OPT_EXPR pass (perform const folding).

4.9. Finished OPT passes. (There is nothing left to do.)

Executing TECHMAP pass (map to technology primitives). 5.1. Executing Verilog-2005 frontend. Parsing Verilog input from ' to AST representation. Generating RTLIL representation for module _90_simplemap_bool_ops'. Generating RTLIL representation for module _90_simplemap_reduce_ops'. Generating RTLIL representation for module _90_simplemap_logic_ops'. Generating RTLIL representation for module _90_simplemap_compare_ops'. Generating RTLIL representation for module _90_simplemap_various'. Generating RTLIL representation for module _90_simplemap_registers'. Generating RTLIL representation for module _90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module _90_shift_shiftx'. Generating RTLIL representation for module _90_fa'. Generating RTLIL representation for module _90_lcu'. Generating RTLIL representation for module _90_alu'. Generating RTLIL representation for module _90_macc'. Generating RTLIL representation for module _90_alumacc'. Generating RTLIL representation for module \$div_mod_u'. Generating RTLIL representation for module $div_mod'. Generating RTLIL representation for module _90_div'. Generating RTLIL representation for module _90_mod'. Generating RTLIL representation for module _90_pow'. Generating RTLIL representation for module _90_pmux'. Generating RTLIL representation for module `_90_lut'. Successfully finished Verilog frontend. Mapping foo.$and$foo.v:8$1 ($and) with simplemap. Mapping foo.$or$foo.v:8$2 ($or) with simplemap. No more expansions possible.

Executing OPT pass (performing simple optimizations). 6.1. Executing OPT_EXPR pass (perform const folding).

6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports.

6.4. Executing OPTREDUCE pass (consolidate $mux and $reduce inputs). Optimizing cells in module \foo. Performed a total of 0 changes.

6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells.

6.6. Executing OPT_RMDFF pass (remove dff with constant values).

6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo..

6.8. Executing OPT_EXPR pass (perform const folding).

6.9. Finished OPT passes. (There is nothing left to do.)

7.Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). ERROR: Syntax error in line 73.

the tcl can run correctly with qflow lib osu018.lib but occur error with tmsc lib,So i wonder if the qfow can support other lib? PS: Syntax error in line 73 come from which script? dfflibmap.cc??