outputprep failure: No file map9v3_mapped.v.

[cheyao]

So I am just running the test tutorial file in qflow (the test tab in http://opencircuitdesign.com/qflow/), and in the syntehes step, it just stays in in progress

and if i click in progress, it says

ERROR: init_share_dirname: unable to determine share/ directory!
outputprep failure:  No file map9v3_mapped.v.
Premature exit.
Synthesis flow stopped due to error condition.

How do I fix this?

synth.log:

Qflow synthesis logfile created on Tue Nov 1 10:09:28 CET 2022
Running yosys for verilog parsing and synthesis
yosys  -s map9v3.ys

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.13+15 (git sha1 bc027b2ca, gcc 13.0.0 -fPIC -Os)

-- Executing script file `map9v3.ys' --

1. Executing Liberty frontend.
Imported 39 cell types from liberty file.

2. Executing Verilog-2005 frontend: /Users/ray/test/cpu/source/main.v
Parsing Verilog input from `/Users/ray/test/cpu/source/main.v' to AST representation.
Generating RTLIL representation for module `\map9v3'.
Successfully finished Verilog frontend.

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \map9v3

3.1.2. Analyzing design hierarchy..
Top module:  \map9v3
Removed 0 unused modules.

3.2. Executing PROC pass (convert processes to netlists).

3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 5 switch rules as full_case in process $proc$/Users/ray/test/cpu/source/main.v:37$1 in module map9v3.
Removed a total of 0 dead cases.

3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

3.2.4. Executing PROC_INIT pass (extract init attributes).

3.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \reset in `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.

3.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
     1/14: $0\dp[8:0] [8:1]
     2/14: $0\dp[8:0] [0]
     3/14: $0\sr[7:0] [0]
     4/14: $0\sr[7:0] [2]
     5/14: $0\sr[7:0] [3]
     6/14: $0\sr[7:0] [4]
     7/14: $0\sr[7:0] [5]
     8/14: $0\sr[7:0] [6]
     9/14: $0\sr[7:0] [7]
    10/14: $0\state[2:0]
    11/14: $0\startbuf[1:0]
    12/14: $0\counter[7:0]
    13/14: $0\done[0:0]
    14/14: $0\sr[7:0] [1]

3.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

3.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\map9v3.\dp' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$119' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\done' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$120' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\counter' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$121' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\sr' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$122' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\startbuf' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$123' with positive edge clock and positive level reset.
Creating register for signal `\map9v3.\state' using process `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
  created $adff cell `$procdff$124' with positive edge clock and positive level reset.

3.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 7 empty switches in `\map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
Removing empty process `map9v3.$proc$/Users/ray/test/cpu/source/main.v:37$1'.
Cleaned up 7 empty switches.

3.2.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.
<suppressed ~3 debug messages>

3.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 0 unused cells and 50 unused wires.
<suppressed ~1 debug messages>

3.5. Executing CHECK pass (checking for obvious problems).
Checking module map9v3...
Found and reported 0 problems.

3.6. Executing OPT pass (performing simple optimizations).

3.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~13 debug messages>

3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.6.6. Executing OPT_DFF pass (perform DFF optimizations).

3.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.6.9. Finished OPT passes. (There is nothing left to do.)

3.7. Executing FSM pass (extract and optimize FSM).

3.7.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register map9v3.state.

3.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\state' from module `\map9v3'.
  found $adff cell for state register: $procdff$124
  root of input selection tree: $0\state[2:0]
  found reset state: 3'000 (from async reset)
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:50$3_Y
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:56$6_Y
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:70$13_Y
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:75$14_Y
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:79$15_Y
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:80$16_Y
  found state code: 3'100
  found state code: 3'011
  found ctrl input: $eq$/Users/ray/test/cpu/source/main.v:66$12_Y
  found state code: 3'010
  found state code: 3'001
  found ctrl output: $eq$/Users/ray/test/cpu/source/main.v:50$3_Y
  found ctrl output: $eq$/Users/ray/test/cpu/source/main.v:56$6_Y
  found ctrl output: $eq$/Users/ray/test/cpu/source/main.v:70$13_Y
  found ctrl output: $eq$/Users/ray/test/cpu/source/main.v:75$14_Y
  found ctrl output: $eq$/Users/ray/test/cpu/source/main.v:79$15_Y
  ctrl inputs: { $eq$/Users/ray/test/cpu/source/main.v:80$16_Y $eq$/Users/ray/test/cpu/source/main.v:66$12_Y }
  ctrl outputs: { $eq$/Users/ray/test/cpu/source/main.v:79$15_Y $eq$/Users/ray/test/cpu/source/main.v:75$14_Y $eq$/Users/ray/test/cpu/source/main.v:70$13_Y $eq$/Users/ray/test/cpu/source/main.v:56$6_Y $eq$/Users/ray/test/cpu/source/main.v:50$3_Y $0\state[2:0] }
  transition:      3'000 2'-- ->      3'001 8'00001001
  transition:      3'100 2'0- ->      3'100 8'10000100
  transition:      3'100 2'1- ->      3'000 8'10000000
  transition:      3'010 2'-- ->      3'011 8'00100011
  transition:      3'001 2'-0 ->      3'001 8'00010001
  transition:      3'001 2'-1 ->      3'010 8'00010010
  transition:      3'011 2'-- ->      3'100 8'01000100

3.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$125' from module `\map9v3'.

3.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 13 unused cells and 13 unused wires.
<suppressed ~14 debug messages>

3.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$125' from module `\map9v3'.
  Removing unused output signal $0\state[2:0] [0].
  Removing unused output signal $0\state[2:0] [1].
  Removing unused output signal $0\state[2:0] [2].
  Removing unused output signal $eq$/Users/ray/test/cpu/source/main.v:79$15_Y.

3.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\state$125' from module `\map9v3' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ----1
  100 -> ---1-
  010 -> --1--
  001 -> -1---
  011 -> 1----

3.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\state$125' from module `map9v3':
-------------------------------------

  Information on FSM $fsm$\state$125 (\state):

  Number of input signals:    2
  Number of output signals:   4
  Number of state bits:       5

  Input signals:
    0: $eq$/Users/ray/test/cpu/source/main.v:66$12_Y
    1: $eq$/Users/ray/test/cpu/source/main.v:80$16_Y

  Output signals:
    0: $eq$/Users/ray/test/cpu/source/main.v:50$3_Y
    1: $eq$/Users/ray/test/cpu/source/main.v:56$6_Y
    2: $eq$/Users/ray/test/cpu/source/main.v:70$13_Y
    3: $eq$/Users/ray/test/cpu/source/main.v:75$14_Y

  State encoding:
    0:    5'----1  <RESET STATE>
    1:    5'---1-
    2:    5'--1--
    3:    5'-1---
    4:    5'1----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'--   ->     3 4'0001
      1:     1 2'1-   ->     0 4'0000
      2:     1 2'0-   ->     1 4'0000
      3:     2 2'--   ->     4 4'0100
      4:     3 2'-1   ->     2 4'0010
      5:     3 2'-0   ->     3 4'0010
      6:     4 2'--   ->     1 4'1000

-------------------------------------

3.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\state$125' from module `\map9v3'.

3.8. Executing OPT pass (performing simple optimizations).

3.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.
<suppressed ~4 debug messages>

3.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~12 debug messages>

3.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.8.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$122 ($adff) from module map9v3 (D = $0\sr[7:0], Q = \sr).
Adding EN signal on $procdff$121 ($adff) from module map9v3 (D = $0\counter[7:0], Q = \counter).
Adding EN signal on $procdff$120 ($adff) from module map9v3 (D = $0\done[0:0], Q = \done).
Adding EN signal on $procdff$119 ($adff) from module map9v3 (D = { \sr \N [0] }, Q = \dp).

3.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 6 unused cells and 15 unused wires.
<suppressed ~7 debug messages>

3.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.
<suppressed ~3 debug messages>

3.8.9. Rerunning OPT passes. (Maybe there is more to do..)

3.8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~10 debug messages>

3.8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.8.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

3.8.13. Executing OPT_DFF pass (perform DFF optimizations).

3.8.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

3.8.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.8.16. Rerunning OPT passes. (Maybe there is more to do..)

3.8.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~10 debug messages>

3.8.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.8.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.8.20. Executing OPT_DFF pass (perform DFF optimizations).

3.8.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.8.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.8.23. Finished OPT passes. (There is nothing left to do.)

3.9. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 bits (of 32) from port A of cell map9v3.$sub$/Users/ray/test/cpu/source/main.v:51$4 ($sub).
Removed top 23 bits (of 32) from port Y of cell map9v3.$sub$/Users/ray/test/cpu/source/main.v:51$4 ($sub).
Removed top 30 bits (of 32) from port B of cell map9v3.$add$/Users/ray/test/cpu/source/main.v:51$5 ($add).
Removed top 24 bits (of 32) from port Y of cell map9v3.$add$/Users/ray/test/cpu/source/main.v:51$5 ($add).
Removed top 24 bits (of 32) from port A of cell map9v3.$add$/Users/ray/test/cpu/source/main.v:51$5 ($add).
Removed top 31 bits (of 32) from port B of cell map9v3.$sub$/Users/ray/test/cpu/source/main.v:65$11 ($sub).
Removed top 24 bits (of 32) from port Y of cell map9v3.$sub$/Users/ray/test/cpu/source/main.v:65$11 ($sub).
Removed top 1 bits (of 2) from port B of cell map9v3.$eq$/Users/ray/test/cpu/source/main.v:80$16 ($eq).
Removed cell map9v3.$procmux$36 ($mux).
Removed cell map9v3.$procmux$42 ($mux).
Removed cell map9v3.$procmux$48 ($mux).
Removed cell map9v3.$procmux$54 ($mux).
Removed cell map9v3.$procmux$60 ($mux).
Removed cell map9v3.$procmux$66 ($mux).
Removed cell map9v3.$procmux$72 ($mux).
Removed cell map9v3.$procmux$96 ($mux).
Removed top 1 bits (of 3) from port B of cell map9v3.$auto$opt_dff.cc:198:make_patterns_logic$164 ($ne).
Removed cell map9v3.$procmux$102 ($mux).
Removed cell map9v3.$procmux$105 ($mux).
Removed cell map9v3.$procmux$108 ($mux).
Removed cell map9v3.$procmux$114 ($mux).
Removed top 1 bits (of 9) from port Y of cell map9v3.$sub$/Users/ray/test/cpu/source/main.v:51$4 ($sub).
Removed top 24 bits (of 32) from wire map9v3.$add$/Users/ray/test/cpu/source/main.v:51$5_Y.
Removed top 24 bits (of 32) from wire map9v3.$sub$/Users/ray/test/cpu/source/main.v:51$4_Y.

3.10. Executing PEEPOPT pass (run peephole optimizers).

3.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

3.12. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module map9v3:
  creating $macc model for $add$/Users/ray/test/cpu/source/main.v:51$5 ($add).
  creating $macc model for $sub$/Users/ray/test/cpu/source/main.v:51$4 ($sub).
  creating $macc model for $sub$/Users/ray/test/cpu/source/main.v:65$11 ($sub).
  merging $macc model for $sub$/Users/ray/test/cpu/source/main.v:51$4 into $add$/Users/ray/test/cpu/source/main.v:51$5.
  creating $alu model for $macc $sub$/Users/ray/test/cpu/source/main.v:65$11.
  creating $macc cell for $add$/Users/ray/test/cpu/source/main.v:51$5: $auto$alumacc.cc:365:replace_macc$178
  creating $alu cell for $sub$/Users/ray/test/cpu/source/main.v:65$11: $auto$alumacc.cc:485:replace_alu$179
  created 1 $alu and 1 $macc cells.

3.13. Executing SHARE pass (SAT-based resource sharing).

3.14. Executing OPT pass (performing simple optimizations).

3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~10 debug messages>

3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.14.6. Executing OPT_DFF pass (perform DFF optimizations).

3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

3.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.14.9. Rerunning OPT passes. (Maybe there is more to do..)

3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~10 debug messages>

3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.14.13. Executing OPT_DFF pass (perform DFF optimizations).

3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.14.16. Finished OPT passes. (There is nothing left to do.)

3.15. Executing MEMORY pass.

3.15.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

3.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

3.15.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

3.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.15.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.15.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.15.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.15.9. Executing MEMORY_COLLECT pass (generating $mem cells).

3.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.17. Executing OPT pass (performing simple optimizations).

3.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.
<suppressed ~1 debug messages>

3.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

3.17.3. Executing OPT_DFF pass (perform DFF optimizations).

3.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

3.17.5. Finished fast OPT passes.

3.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

3.19. Executing OPT pass (performing simple optimizations).

3.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \map9v3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~9 debug messages>

3.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \map9v3.
Performed a total of 0 changes.

3.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\map9v3'.
Removed a total of 0 cells.

3.19.6. Executing OPT_SHARE pass.

3.19.7. Executing OPT_DFF pass (perform DFF optimizations).

3.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \map9v3..

3.19.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module map9v3.

3.19.10. Finished OPT passes. (There is nothing left to do.)

3.20. Executing TECHMAP pass (map to technology primitives).
ERROR: init_share_dirname: unable to determine share/ directory!
outputprep failure:  No file map9v3_mapped.v.
Premature exit.
Synthesis flow stopped due to error condition.

[cheyao]

I've fixed it by running it in the terminal, but now on the place step, i get the error dlopen(/usr/local/share/qrouter/qrouter.so, 5) How can i fix this?