Closed santosh2407 closed 6 months ago
Even I have the same issue please u found solution let me know
This is due to the potential errors in the Verilog file. Please make sure that the verilog file simulated in Linux Environment. You can use iVerilog for the same.
I am having error in synthesis process Qflow synthesis failed to generate an output .blif file
I have installed all the required packages and tools for running Qflow but after opening the gui and uploading the verilog file, the first step "Preparation" is running successfully when I'm running the synthesis process it is throwing an error saying "errors encountered in synthesis flow", "Qflow synthesis failed to generate and output .v file."
Please help me out!