Issue in Ones and Zeros Counter

RadioactiveScandium / Digital-Logic-Design

Digital logic implementation and verification through Verilog/SV

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Issue in Ones and Zeros Counter #11

Open RadioactiveScandium opened 3 months ago

RadioactiveScandium commented 3 months ago

In the RTL code, output is used as input without using any flop. Even though this code might be functionally correct, there might be potential combo loops in the design . Check and fix.