RadioactiveScandium / Digital-Logic-Design

Digital logic implementation and verification through Verilog/SV
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Add code/TB for Round Robin Arbiters #7

Closed RadioactiveScandium closed 3 months ago

RadioactiveScandium commented 3 months ago

Refer the directory for Fixed Priority Arbiter and follow suit.

RadioactiveScandium commented 3 months ago

Untested code pushed into the placeholder. Verify the design.

RadioactiveScandium commented 3 months ago

Verified code and testbench pushed into the repo. Closing this issue