RadioactiveScandium / Digital-Logic-Design

Digital logic implementation and verification through Verilog/SV
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Coding using macros #8

Open RadioactiveScandium opened 3 months ago

RadioactiveScandium commented 3 months ago

Start migrating to usage of macros across all designs, wherever applicable. Macros enable seamless and diligent reuse of frequently used design elements, while improving code readability at the same time. For example, below is a flop macro which could be used across many RTL codes :

// D flip-flop w/ async reset_n
`define DFF_ARN(q, d, en, clk, rst_n) \
always_ff @(posedge clk or negedge rst_n) begin \
    if (!rst_n) q <= '0; \
    else  if(en)      q <= d; \
    else              q <= q; \   
end

Usage of the above macro is shown as follows :

`DFF_ARN(out, in, enable, clkin, rstn);

User must pass the arguments to the macro carefully to ensure correct functionality.