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Rakete1111 / sdcc-pdk

SDCC branch for the pdk arch
GNU General Public License v2.0
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idxm encoding #3

Closed cpldcpu closed 5 years ago

cpldcpu commented 5 years ago

https://github.com/Rakete1111/sdcc-pdk/blob/927264c1e9a893fec38d4dd402a3661a16bfa7c6/sdas/aspdk/pdkmch.c#L92

and mask should be 7e? Something is fishy about the instruction set encoding here. Is the address shifted or is the LSB discarded?

cpldcpu commented 5 years ago

Another potential bug:

https://github.com/Rakete1111/sdcc-pdk/blob/927264c1e9a893fec38d4dd402a3661a16bfa7c6/sdas/aspdk/pdkmch.c#L316

opcode encoding for ret # is missing here (0x0200)

cpldcpu commented 5 years ago

https://github.com/Rakete1111/sdcc-pdk/blob/927264c1e9a893fec38d4dd402a3661a16bfa7c6/sdas/aspdk/pdkmch.c#L377

and mask should be 0x7E. Alternatively there is a left shift missing.

Rakete1111 commented 5 years ago

and mask should be 7e? Something is fishy about the instruction set encoding here. Is the address shifted or is the LSB discarded?

Oh yeah that's fishy :). It's missing a left shift by one.

opcode encoding for ret # is missing here (0x0200)

oh yeah; I remember thinking about that... Must have dropped it or something. Thanks

and mask should be 0x7E. Alternatively there is a left shift missing.

the left shift again...

Thank you and sorry for the wait.

cpldcpu commented 5 years ago

@Rakete1111

According to information by Opossum in the EEV forum, the LSB of the memory location is discarded. Therefore the address for IDXM/LDT/STT should be calculated as below, without a shift:

op |= e.e_addr & 0x7E;

https://www.eevblog.com/forum/blog/eevblog-1144-padauk-programmer-reverse-engineering/msg2153626/#msg2153626

Rakete1111 commented 5 years ago

I'm afraid I don't understand. Memory is RAM right, so there are 128 bytes of RAM that are AFAICT byte aligned (why word aligned?) which would mean that only 7 bits are required. There should be no bits discarded.

Rakete1111 commented 5 years ago

Although I just noticed that there are some instructions (SET, TSN) that do use a 6 bit memory address. So in that case I'd imagine that the MSB is discarded.

cpldcpu commented 5 years ago

yes, but there are actually only 6 bits to encode the memory address in IDXM/LDT/STT (0x7e=6 bits set!). Hardwiring the LSB of the address to 0 allows accessing all 128 memory locations.

Rakete1111 commented 5 years ago

Ahh got it, thanks!