Remove duplicate models by loading the liberty ones

[pepijndevos]

When simulating generated designs by generating verilog models for the liberty cells, I ran into conflicts between the verilog and liberty models. But yosys can load the liberty models, so the verilog ones can be removed.

[pepijndevos]

Eh... I pushed the simulation stuff here as well because it depends on the other changes so things would be a hassle with branches.

As noted in commit message, picorv32 simulation basically does not finish correctly, so there is a bug somewhere.

[pepijndevos]

Gtkwave seems to show that cpuregs_rs1 is where the firs XX shows up, although some lines are just XX from the start, which... maybe more likely to be the real source of trouble. But oddly enough a few lines are XX in the original but not in the 74xx version.

[pepijndevos]

So it turns out that after I removed the verilog mux models, I did not update the techpass to match the liberty portmap. This lead to nothing being connected and everything being optimized away. Needless to say things work much better now. Have not yet checked if the output is actually correct, but at least there is some output.

[pepijndevos]

Wooohooo, picorv32 and all the other things I've checked so far seem to simulate correctly now. The mux liberty file had the selection pins reversed from the datasheet.

[pepijndevos]

This is it for now.