Generate KiCad netlists

[pepijndevos]

I made some initial progress towards generating KiCad netlists from Verilog. It's still very WIP, as it only supports the adder and flip-flop needed for the counter benchmark (when you remove the reset part) It also quite liberally uses the "wrong" part for the dff, but functionally it should be fine. Stuff left to do:

• [x] Add all the chips (or the closest functional equivalent)
• [x] Refactor nicely
• [ ] Find/make libraries for the correct parts
• [x] Solve innocent ERC errors so that actual errors are clear

Progress on the chips:

• [x] 74AC02_4x1NOR2
• [x] 74AC10_3x1NAND3
• [x] 74AC11000_4x1NAND2
• [x] 74AC11004_6x1NOT
• [x] 74AC11008_4x1AND2
• [x] 74AC11032_4x1OR2
• [x] 74AC11074_2x1DFFSR
• [x] 74AC11086_4x1XOR2
• [x] 74AC11244_8x1BUF
• [x] 74AC11257_4x1MUX2
• [x] 74AC11_3x1AND3
• [x] 74AC151_1x1MUX8
• [x] 74AC151_1x1MUXI8
• [x] 74AC153_2x1MUX4
• [x] 74AC158_4x1MUXI2
• [x] 74AC16374_16x1DFF (74LS374 used)
• [x] 74AC20_2x1NAND4
• [x] 74AC283_1x1ADD4
• [x] 74AC377_8x1DFFE
• [x] 74HC688_1x1EQ8
• [x] 74HC85_1x1CMP4
• [x] 74AC273_8x1DFFR

[pepijndevos]

Look at this beauty!

[pepijndevos]

This contains functional equivalents of all chips now, and can generate a netlist for all benchmarks in theory. It's just really slow for the larger benchmarks. Right now using "classic" pinouts for 74AC11 parts, and the 8-bit version of the 74AC16 DFF.

I think it's OK to merge this now. I will come back to the ERC warnings and 74AC11 series another time. Time to fix some bugs and start building that bit-serial CPU. Would simplify my git branch jungle a bit if this stuff was on master.

[pepijndevos]

Actually, fixing ERC seems pretty easy, will do that tonight https://github.com/xesscorp/skidl/issues/61#issuecomment-510848610