Improve reset synthezation

[pepijndevos]

When I synthesize a simple counter, I get pretty much what you'd expect

 \74AC16374_16x1DFF              9
 \74AC283_1x1ADD4                2

But when using a reset, a lot of extra stuff is generated. For active-high synchronous reset it basically uses muxes and a bunch of random things.

 \74AC02_4x1NOR2                 8
 \74AC11004_6x1NOT               8
 \74AC11257_4x1MUX2              1
 \74AC16374_16x1DFF              9
 \74AC283_1x1ADD4                2

For asynchronous active low reset, it does a lot better and actually uses the resettable DFF, but with 2 flip-flops in a 14 pin package, it's not very efficient:

 \74AC11074_2x1DFFSR             8
 \74AC16374_16x1DFF              1
 \74AC283_1x1ADD4                2

So there are two ways I think we can do better:

For synchronous reset, it'd be useful to find a DFF that supports it. The liberty syntax seems to be as follows, but Yosys says it's not supported.

ff(IQ, IQN) {
    next_state : "D * CLR";
    clocked_on : "CP" ;
}

There are a large variety of chips that have a common clear. I would say the common case for a reset is to set everything to zero, so if there is a way to teach Yosys about them, it'd be a lot more efficient.

Some candidates I've found:

74x575 octal D-type edge-triggered flip-flop, synchronous clear 74x273 8-bit register, asynchronous clear

I added the 74x273. However, it seems the 575 is not in production anywhere. So I guess the conclusion is, don't do synchronous reset in 74xx logic.

I've also updated the area of some chips to account for shared pins.

What's a bit unfortunate is that the 74AC11074 has a inverted output that ABC won't like. Would it make sense to make a copy of it that only exposes the inverted output? Might save a few not gates here and there.

After these changes, the counter with reset results in

 \74AC273_8x1DFFR                8
 \74AC283_1x1ADD4                2