Open zachary-cauchi opened 4 months ago
Hi @Ravenslofty. Managed to get a basic panic handler set up and printing out a core dump of the implemented CoP0 registers. I'm now looking into how to set up exception handlers for the lower-level exceptions but I'm a bit confused. Based on what I read in the EE Core User's Manual, and assuming I'm understanding right, the PS2 will call exception handlers found at specific address and it is there thatwe follow the procedure outlined in chapters 4.1.2 and 4.1.3. Is that more or less corect?
Yes, that's correct.
(Though for the sake of clarity, when the manual says "the following processes are executed", it's referring to the CPU executing them, rather than user code needing to do this.)
Ah okay, that makes sense. Thanks. I'll next work on getting an exception handler set up and printing a similar coredump to the panic handler. Presumably, I'll need to make changes to hte linkfile to get the function located at the correct memory address. Will keep you posted here on any updates/challenges.
Do keep in mind that you're working in an interrupt context when doing so. That means things like disabling interrupts at the start of the handler, and being mindful of saving registers if necessary.
Also, while you can just hexdump the exception registers, MIPS has a sneaky trick: Cause.ExcCode
is offset by two bits, which means if you AND it with, say, 0xFF
, you get a table offset you can add to a base to index a jump table. That lets you quickly dispatch to a specific handler based on the exception code.
Ah I see, hadn't thought of that. Thanks, will take the precautions. That's pretty neat, will be sure to implement that! Thanks!
With #19 merged in, we now have access to the CoP0 exception-related registers, meaning we can create basic exception-handling.
Definition of Done:
EEOut
.