Too case sensitive - Githubissues

In the following code, when the component PseudoTosNet_ctrl is defined, something in the syntax recognition goes wrong. I assume that 'END' is not recognised as 'end', as changing from uppercase to lowercase solves the problem.

The original code compiles just fine. ISE recognises the syntax just fine.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PTNX_top is      -- PTNX = "Pseudo TosNet eXample"
Port(
    CLK_50M_I       : in    STD_LOGIC;
    LEDS_O          : out   STD_LOGIC_VECTOR(1 downto 0);

    XB_SERIAL_O     : out   STD_LOGIC;
    XB_SERIAL_I     : in    STD_LOGIC;

    PULSE_I         : in    std_logic;
    PULSE_O         : out   std_logic;
    DATA_O          : out   STD_LOGIC_VECTOR(7 downto 0)
);
end PTNX_top;

architecture Behavioral of PTNX_top is

COMPONENT PseudoTosNet_ctrl IS
Port(
    T_clk_50M               : in    STD_LOGIC;
    T_serial_out            : out   STD_LOGIC;
    T_serial_in             : in    STD_LOGIC;
    T_reg_ptr               : out   std_logic_vector(2 downto 0);
    T_word_ptr              : out   std_logic_vector(1 downto 0);
    T_data_to_mem           : in    std_logic_vector(31 downto 0);
    T_data_from_mem         : out   std_logic_vector(31 downto 0);
    T_data_from_mem_latch   : out   std_logic
    );
END COMPONENT;

-- These lines are inserted to show that syntax colouring is off.
signal clk_50M           : std_logic;
signal sys_cnt              : std_logic_vector(31 downto 0) := (others => '0');

Razer6 / language-vhdl

Too case sensitive #7