search

Remillard / VHDL-Mode

A package for Sublime Text that aids coding in the VHDL language.
MIT License
39 stars 10 forks source link

More Assignment Alignment Issues #126

Closed Remillard closed 5 years ago

Remillard commented 5 years ago

The following will not align <= likely due to an interaction with when

    ch1_cw_i_val <= '0' & discretes_ctrl.tx_output_gain(15 downto 1) when iq_select = '0' else (others => '0');
    ch1_cw_q_val <= '0' & discretes_ctrl.tx_output_gain(15 downto 1) when iq_select = '1' else (others => '0');
    ch2_cw_val <= '0' & discretes_ctrl.tx_output_gain(15 downto 1);
    ch3_cw_val <= '0' & discretes_ctrl.tx_output_gain(15 downto 1);
Remillard commented 5 years ago

It is specifically due to when followed by a => symbol.

Adding a fix where it explicitly looks for when <choice> => where the => must be followed by whitespace to the end of the line. This does fix it but might cause some other weird behaviors. Will have to keep an eye on it.