Remillard / VHDL-Mode

A package for Sublime Text that aids coding in the VHDL language.
MIT License
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Alignment in Paste as Signal #13

Closed Remillard closed 7 years ago

Remillard commented 7 years ago

When using paste as signal, the alignment seems to fail on the final line. A sample:

    -- Testbench signals
    signal clk               : std_logic;
    signal reset             : std_logic;
    signal ttimer_ext_rst    : std_logic;
    signal ttimer_ext_rst_en : std_logic;
    signal tick_timer        : std_logic_vector(31 downto 0);
    signal tick10_irq        : std_logic;
    signal ttimer_rst_irq : std_logic ;
Remillard commented 7 years ago

Fixed alignment in 1.1.1, and also fixed that little spacing issue there with the final semicolon.