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Remillard / VHDL-Mode

A package for Sublime Text that aids coding in the VHDL language.
MIT License
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Strange and incorrect beautification #157

Open Remillard opened 4 years ago

Remillard commented 4 years ago

Found this happening, not sure why it's happening and not a lot of time to debug at the moment: 

entity asdf is
    port (

    );
end entity asdf;

​entity register is
port (
    A   : in  std_logic_vector(7 downto 0);
    clk : in  std_logic;
    clr : in  std_logic;
    B   : out std_logic_vector(7 downto 0)
);
end register;

Note that the port clause in the second entity isn't indenting

Remillard commented 4 years ago

Okay, figured a partial out. If the entity is the first character of the buffer, it doesn't identify it correctly. However in the example, it's not the first character of the buffer so ... not sure what's going on here. It just evaluates as default.

Remillard commented 4 years ago

I think it has something to do with using ^entity as the pattern. I altered it to excluding end and without the line anchor and it seems to fix everything. Will have to play with it a little more before I trust this completely.

Remillard commented 4 years ago

Had same issue on architecture just now. Came from importing some badly formatted student code and again architecture wasn't being evaluated until I lost the leading line anchor and put in the (?<!end ) part. Wonder if there was a hidden character in there somewhere.

Remillard commented 4 years ago

However this solution seems to screw up component direct entity instantiation, so undoing this for now and will have to investigate further when I can.