Syntax scoping error

[Remillard]

Syntax for component seems broken if a few options are left out. I think they're mandatory in VHDL-2008, but clearly not for prior versions of the language -- or my reference did not mark these words as optional. Anyhow, the following does not scope correctly:

    component tacan_ident
        port (
            ARB             : in  std_logic;
            CE              : in  std_logic;
            clk_80          : in  std_logic;
            ident_en        : in  std_logic;
            ident_en_edge   : in  std_logic;
            tacan_mode      : in  std_logic_vector (6 downto 0);
            tacan_mode_edge : in  std_logic;
            id_P_trigger    : out std_logic;
            id_S_trigger    : out std_logic;
            id_window       : out std_logic
        );
    end component;

The problem seems to be the inclusion of the word is after the component identifier, and the inclusion of the component identifier in the end clause.

[Remillard]

Fixed and staged for release.