Circuits need to be able to be compiled to match the gatesets of specific hardware implementations - furthermore there should be the ability to optimize circuits to reduce gate counts (weighted by the difficulty for each).
In general this problem is intractable, but simulated annealing is reasonably good at it.
Circuits need to be able to be compiled to match the gatesets of specific hardware implementations - furthermore there should be the ability to optimize circuits to reduce gate counts (weighted by the difficulty for each). In general this problem is intractable, but simulated annealing is reasonably good at it.