Reservoir-In-Processor / rip-sim

Cycle-level simulator for "Reservoir in Processor"
Apache License 2.0
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[RIPSim & Sim] check dhrystone is correctly finished #82

Closed khei4 closed 10 months ago

khei4 commented 11 months ago

https://github.com/YosysHQ/picorv32/blob/f00a88c36eaab478b64ee27d8162e421049bcc66/dhrystone/start.S#L37-L50

We can see 'DONE' in registers?

khei4 commented 11 months ago

I found picorv32 uses original stdlib by default, but we can use picorv32 stdlib and startup by setting flag. https://github.com/YosysHQ/picorv32/blob/f00a88c36eaab478b64ee27d8162e421049bcc66/dhrystone/Makefile#L6-L8