RoaLogic / RV12

RISC-V CPU Core
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sim: drop Icarus Verilog stuff #17

Closed frantony closed 6 years ago

frantony commented 6 years ago

All Roa Logic IP is written in System Verilog which is unfortunately not supported by Icarus.

See https://github.com/RoaLogic/RV12/issues/15 for details.

Signed-off-by: Antony Pavlov antonynpavlov@gmail.com

sphardy commented 6 years ago

Spurious Icarus support files removed by Richard - no need to merge pull request