about the core simulation

[youping2009]

I got the below error when I run the simulation. Why? Thanks! make SIM=vcs find: /data_n3xs/ip_lib': No such file or directory make vcs LOG=./log/DCACHE_SIZE0@ICACHE_SIZE0@MEM_LATENCY0@WRITEBUFFER_SIZE0@XLEN32@rv32ui-p-simple.log \ PARAMS="DCACHE_SIZE=0 \ ICACHE_SIZE=0 \ MEM_LATENCY=0 \ WRITEBUFFER_SIZE=0 \ XLEN=32 \ MULT_LATENCY=rv32ui-p-simple \ HAS_U=1 HAS_S=1 HAS_H=0 \ HAS_AMO=0 HAS_RVC=0 HAS_MULDIV=1 \ TECHNOLOGY=n3xs \ INIT_FILE=\"../../../../../bench/regression/rv32ui-p-simple.hex\" " find:/data_n3xs/ip_lib': No such file or directory make[1]: Entering directory /RV12-master/sim/ahb3lite/regression/run' make[2]: Entering directory/RV12-master/sim/ahb3lite/regression/run/vcs'

Warning-[LCA_FEATURES_ENABLED] Usage warning LCA features enabled by '-lca' argument on the command line. For more information regarding list of LCA features please refer to Chapter "LCA features" in the VCS/VCS-MX Release Notes

Error-[SE] Syntax error Following verilog source has syntax error : "/RV12-master/rtl/verilog/pkg/riscv_pkg.sv", 44: token is ';' package riscv_pkg; ^

1 warning 1 error make[2]: [sim] Error 255 make[2]: Leaving directory `/RV12-master/sim/ahb3lite/regression/run/vcs' make[1]: [vcs] Error 2 make[1]: Leaving directory `/RV12-master/sim/ahb3lite/regression/run' make: *** [DCACHE_SIZE0@ICACHE_SIZE0@MEM_LATENCY0@WRITEBUFFER_SIZE0@XLEN32@rv32ui-p-simple.log] Error 2

[youping2009]

fixed. add the vcs compile option -sverilog