Reading MCYCLE causes trap

[drichmond]

Reading MCYCLE (with HAS_* = 0) causes the processor to enter the RISC-V trap.

I believe it's caused by missing checks in the case statement in https://github.com/RoaLogic/RV12/blob/fdf1e834d91649c1d14f51ab33105bde45ef25e3/rtl/verilog/core/riscv_id.sv#L670

If I add the following lines the trap goes away:

MCYCLE    : illegal_csr_rd =                                  (st_prv < PRV_M);
MINSTRET  : illegal_csr_rd =                                  (st_prv < PRV_M);                                                                                                                                                                                                         
MCYCLEH   : illegal_csr_rd =                    (XLEN > 32) | (st_prv < PRV_M);
MINSTRETH : illegal_csr_rd =                    (XLEN > 32) | (st_prv < PRV_M);

These mimic the lines from the illegal_csr_wr case statement later in the file.

Can make a PR if desired but I want to check that this isn't intentional first.

[rherveille]

This is a confirmed bug. I already implemented the fix and will update GitHub later today.